• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2005년도 춘계학술대회
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• pp.102-108
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• 2005

We have developed highly stabilized (p-i-n)-type protocrystalline silicon (pc-Si:H) multilayer solar cells. To achieve a high conversion efficiency, we applied a double-layer p-type amorphous silicon-carbon alloy $(p-a-Si_{1-x}C_x:H)$ structure to the pc-Si:H multilayer solar cells. The less pronounced initial short wavelength quantum efficiency variation as a function of bias voltage proves that the double $(p-a-Si_{1-x}C_x:H)$ layer structure successfully reduces recombination at the p/i interface. It was found that a natural hydrogen treatment involving an etch of the defective undiluted p-a-SiC:H window layer before the hydrogen-diluted p-a-SiC:H buffer layer deposition and an improvement of the order in the window layer. Thus, we achieved a highly stabilized efficiency of $9.0\%$ without any back reflector.

• Restorative Dentistry and Endodontics
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• 제35권1호
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• pp.13-19
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• 2010

이 연구는 다이몬드 포인트와 카바이드 버 및 SiC paper로 삭제한 상아질에 대한 자가부식 프라이머 접착제의 결합강도를 비교하고, 실험실에서 사용하는 SiC paper와 유사한 결합강도를 나타내는 회전용 삭제기구를 알아보기 위하여 시행하였다. 56개의 발거된 대구치 치관의 교합면 상아질을 노출시켜 1.2 mm의 두께의 시편을 제작한 후 8개의 군으로 분류하였다. 1군은 standard diamond point (TF-12), 2군은 fine diamond point (TF-12F). 3군은 extrafine diamond point (TF-12EF), 4군은 cross-cut carbide bur (no. 557), 5군은 plain-cut carbide bur (no. 245), 6군은 P 120-grade SiC paper, 7군은 P 220-grade SiC paper, 8군은 P 800-grade SiC paper를 사용하여 각 시편의 상아질 표면을 약 0.2 mm정도 삭제하였다. 상아질 표면에 Clearfil SE Primer와 Bond를 적용하고 Tygon tube를 이용하여 Clearfil AP-X를 충전하고 40초간 광조사 하였다. 제작된 시편은 만능시험기를 이용하여 를 미세전단 결합강도는 측정한 후, 각 군의 결합강도를 one-way ANOVA와 Tukey검정을 이용하여 분석하여 다음과 같은 결과를 얻었다. 자가부식 프라이머 접착제 사용 시 상아질에 대한 개선된 접착을 위해서는 초미세입자 다이아몬드 포인트의 사용이 추천되며, 실험실적인 연구에서 P 220-grade SiC paper의 사용은 미세입자 다이아몬드 포인트나 카바이드 버로 삭제한 상아질 면과 유사한 결합강도를 나타내었다.

• Advances in nano research
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• 제2권1호
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• pp.23-56
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• 2014

The significant growth of the Si photovoltaic industry has been so far limited due to the high cost of the Si photovoltaic system. In this regard, the most expensive factors are the intrinsic cost of silicon material and the Si solar cell fabrication processes. Conventional Si solar cells have p-n junctions inside for an efficient extraction of light-generated charge carriers. However, the p-n junction is normally formed through very expensive processes requiring very high temperature (${\sim}1000^{\circ}C$). Therefore, several systems are currently under study to form heterojunctions at low temperatures. Among them, carbon nanotube (CNT)/Si hybrid solar cells are very promising, with power conversion efficiency up to 15%. In these cells, the p-type Si layer is replaced by a semitransparent CNT film deposited at room temperature on the n-doped Si wafer, thus giving rise to an overall reduction of the total Si thickness and to the fabrication of a device with cheaper methods at low temperatures. In particular, the CNT film coating the Si wafer acts as a conductive electrode for charge carrier collection and establishes a built-in voltage for separating photocarriers. Moreover, due to the CNT film optical semitransparency, most of the incoming light is absorbed in Si; thus the efficiency of the CNT/Si device is in principle comparable to that of a conventional Si one. In this paper an overview of several factors at the basis of this device operation and of the suggested improvements to its architecture is given. In addition, still open physical/technological issues are also addressed.

• 한국진공학회지
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• 제20권1호
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• pp.50-56
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• 2011

본 논문에서는 버퍼막 두께 및 열처리 온도에 따른 ZnO/b-ZnO/p-Si(111) 기반 이종접합 다이오드 전류 특성에 대한 연구가 진행되었고, b-ZnO (ZnO buffer layer) 버퍼막 두께 및 열처리 온도에 따른 p-Si(111) 기판 위에 증착시킨 ZnO 박막의 구조적, 전기적 특성 또한 연구되었다. X-ray diffraction (XRD) 방법을 이용하여 ZnO 박막의 구조적 특성을 측정하였고, semiconductor parameter analyzer를 이용하여 ZnO/b-ZnO/p-Si(111) 이종접합 다이오드의 I-V 특성을 평가하였다. XRD 분석 결과 버퍼막 열처리 온도 $700^{\circ}C$, 버퍼막 두께 70 nm에서 ZnO 박막은 우세한 (002) 방향의 c-축 배향성을 갖는 육방정계(hexagonal wurtize) 결정 구조를 나타내었다. 전기적 특성인 운반자 농도, 비저항 값의 경우에는 버퍼막 열처리 온도 $700^{\circ}C$, 버퍼막 두께 50 nm에서 우수한 전기적 특성(비저항: $2.58{\times}10^{-4}[{\Omega}-cm]$, 운반자 농도: $1.16{\times}10^{20}[cm^{-3}]$)을 보였다. 또한 ZnO/b-ZnO/p-Si(111) 이종접합 다이오드의 전류 특성은 버퍼막 열처리 온도 $700^{\circ}C$에서 버퍼막 두께가 증가할수록 전류 특성이 향상되는 경향을 보였다.

• 전기학회논문지
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• 제60권1호
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• pp.105-108
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• 2011

Newly-developed fabrication of a p-n heterojunction diode constructed with a p-Si nanowire (NW) and an n-ZnO nanoparticle (NP) thin-film by the dielectrophoresis (DEP) technique is demonstrated in this study. With the bias of 20 Vp-p at the input frequency of 1 MHz, the most efficient assembly of the n-ZnO NPs is shown for the fabrication of the p-n heterojunction diode with a p-Si NW. The p-n heterojunction diode fabricated in this study represents current rectifying characteristics with the turn on voltage of 1.1 V. The diode can be applied to the fabrication of optoelectrical devices such as photodetectors, light-emitting diodes (LEDs), or solar cells based on the high conductivity of the NW and the high surface to volume ratio of the NP thin film.

• 대한전기학회논문지
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• 제41권2호
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• pp.170-177
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• 1992

Contact resistance and contact leakage current of the Al/TiSiS12T/Si system are investigated for NS0+T and PS0+T junctions. SALICIDE (Self Aligned Silicide) process was used to make the Al/TiSiS12T/Si system. Titanium disilicide is one of the most common silicides because of its thermal stability, ability to form selective formation and low resistivity. In this paper, RTA temperature effect and Junction implant dose effect were evaluated to characterize contact resistance and contact leakage current. The TiSiS12T contact resistance to NS0+T silicon is lower than that to PS0+T silicon, and TiSiS12T of contact leakage current to NS0+T silicon is lower than that to PS0+T silicon. Contact resistance and contact leakage current of the Al/TiSiS12T/Si system by this method were possible for VLSI application.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2007년도 춘계학술대회
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• pp.179-182
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• 2007

Polycrystaline (poly) 3C-SiC thin film on n-type and p-type Si were deposited by APCVD using HMDS, $H_2$, and Ar gas at $1180^{\circ}C$ for 3 hour. And then the schottky diode with Au/poly 3C-Sic/Si(n-type) structure was fabricated. Its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) value were measured as 0.84 V, over 140 V, 61nm, and $2.7{\times}10^{19}\;cm^3$, respectively. The p-n junction diode fabricated by poly 3C-SiC was obtained like characteristics of single 3C-SiC p-n junction diode. Therefore, its poly 3C-SiC thin films are suitable MEMS applications in conjuction with Si fabrication technology.

• 센서학회지
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• 제20권3호
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• pp.168-171
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• 2011

Porous 3C-SiC(pSiC) samples with different pore diameters were prepared from poly crystalline N-type 3C-SiC by electrochemical anodization. The pSiC surface was chemically modified by the sputtering of Pd and Pt nano-particles as a hydrogen catalyst. Changes in resistance were monitored with hydrogen concentrations in the range of 110 ppm - 410 ppm. The variations of the electrical resistance in the presence of hydrogen demonstrated that Pd and Pt-deposited pSiC samples have the ability to detect hydrogen at room temperature. Regardless of the catalyst, the 25 nm pore diameter samples showed good response and recovery properties. However, the 60 nm samples showed unstable and slow response. It was found that the pore size affects the catalyst reaction and consequently, results in changes of the sensitivity to hydrogen.

• 한국전기전자재료학회논문지
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• 제11권9호
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• 한국세라믹학회지
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• 제36권6호
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• pp.604-610
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• 1999

Silicide layer structures and morphology degradation of the surface and interface of the silicide layers for he Co/refractory metal bilayer sputter-deposited on the P-doped polycrystalline Si substrate and subjected to rapid thermal annealing were investigated and compared with those on the single Si substrate. The CoSi-CoSi2 phase transition temperature is lower an morphology degradation of the silcide layer occurs more severely for the Co/refractorymetal bilayer on the P-doped polycrystalline Si substrate than on the single Si substrate. Also the final layer structure and the morphology of the films after silicidation annealing was found to depend strongly upon the interlayer metal. The layer structure after silicidation annealing of Co/Hf/doped-poly Si is Co-Hf alloy/polycrystalline CoSi2/poly Si substrate while that of Co/Nb is polycrystalline CoSi2/NbSi2/polycrystalline CoSi2/poly Si.