• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.212-214
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• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.346-349
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• 2002

High Power and high dose ion implantation is essentially needed to make power MOSFET devices based on SiC wafers, because the diffusivities of the impurities such as Al, N, p, B in SiC crystal are very low. In addition, it is needed high temperature annealing for electrical activation of the implanted species. Due to the very high annealing temperature, the surface morphology after electrical activation annealing becomes very rough. We have found the different surface morphologies between implanted and unimplanted region. The unimplanted region showed smoother surface morphology It implies that the damage induced by high energy ion implantation affects the roughening mechanism. Some parts of Si-C bonding are broken in the damaged layer, s\ulcorner the surface migration and sublimation become easy. Therefore the macrostep formation will be promoted. N-type 4H-SiC wafers, which were Al ion implanted at acceleration energy ranged from 30kev to 360kev, were activated at 1600$^{\circ}C$ for 30min. The pre-activation annealing for damage relaxation was performed at 1100-1500$^{\circ}C$ for 30min. The surface morphologies of pre-activation annealed and activation annealed were characterized by atomic force microscopy(AFM).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.349-352
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• 2001

In this paper, novel device structure in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA) for ultra pn junction formation. Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20 nm for arsenic dosage (2$\times$10$^{14}$ $\textrm{cm}^2$), excimer laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.488-491
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• 2006

In this paper proposed method of maximum power point tracking using boost converter for a connected single phase inverter with photovoltaic system. The maximum power point tracking control is based on generated circuit control MOSFET switch of boost converter and single phase inverter uses predicted current control to control four IGBT's switch in full bridge. The predicted current control provide current with sinusoidal wave shape and inphase with voltage. The generation control circuit allows each photovoltaic module to operate independently at peak capacity, simply by detecting of the output power of the system. Furthermore, the generation control circuit attenuates low-frequency ripple voltage, which is caused by the full-bridge inverter, across the photovoltaic modules. Consequently, the output power of system is increased due to the increase in average power generated by the photovoltaic modules. The effectiveness of the proposed inverter system is confirmed experimentally and by means of simulation.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.2148-2150
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• 1998

This paper proposes a constant frequency controlled zero voltage switching method that can reduce switching losses caused by emf on inductance in DC motor. The zero voltage switching method is used more than a zero current switching method because of reducing switching losses by capacitance of depletion region of MOSFET. To simplify the controller circuit, we propose constant frequency controlled zero voltage switching method in the paper. The control method is more stable than a variable frequency control method because it can optimize bandwidth of a closed-loop and reactances. Therefore, we construct a constant frequency controlled zero voltage switching converter and improve zero switching losses in high switching frequency. In the process, we can control low-losses in full range on variable voltage and load. We simulate the proposed converter with P-SPICE and compare results obtained through the experiment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.735-738
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• 2000

This paper shows experimentally that oxide layer on the p-type Si-substrate can grow at low temperature(500$^{\circ}C$∼600$^{\circ}C$) using high pressure water vapor system. As the result of experiment, oxide layer growth rate is about 0.19${\AA}$/min at 500$^{\circ}C$, 0.43${\AA}$/min at 550$^{\circ}C$, 1.2${\AA}$/min at 600$^{\circ}C$ respectively. So, we know oxide layer growth follows reaction-controlled mechanism in given temperature range. Consequently, granting that oxide layer growth rate increases linearly to temperature over 600$^{\circ}C$, we can expect oxide growth rate is 5.2${\AA}$/min at 1000$^{\circ}C$. High pressure oxidation of silicon is particularly attractive for the thick oxidation of power MOSFET, because thermal oxide layers can grow at relatively low temperature in run times comparable to typical high-temperature, 1 atm conditions. For higher-temperature, high-pressure oxidation, the oxidation time is reduced significantly

• Journal of Sensor Science and Technology
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• v.24 no.5
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• pp.353-357
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• 2015

A new SPICE-compatible model for a gate/body-tied PMOSFET photodetector (GBT PD) with an overlapping control gate is presented. The proposed SPICE-compatible model of a GBT PD with an overlapping control gate makes it possible to control the photocurrent. Research into GBT PD modeling was proposed previously. However, the analysis and simulation of GBT PDs is not lacking. This SPICE model concurs with the measurement results, and it is simpler than previous models. The general GBT PD model is a hybrid device composed of a MOSFET, a lateral bipolar junction transistor (BJT), and a vertical BJT. Conventional SPICE models are based on complete depletion approximation, which is more applicable to reverse-biased p-n junctions; therefore, they are not appropriate for simulating circuits that are implemented with a GBT PD with an overlapping control gate. The GBT PD with an overlapping control gate can control the sensitivity of the photodetector. The proposed sensor is fabricated using a $0.35{\mu}m$ two-poly, four-metal standard complementary MOS (CMOS) process, and its characteristics are evaluated.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.241.1-241.1
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• 2013

최근 고집적화된 금속-산화막 반도체 metal oxide semiconductor (MOS) 소자는 크기가 점점 작아짐에 따라 얇은 산화막과 다양한 High-K 물질과 전극에 대하여 연구되고 있다. 이러한 소자의 열적 안정성과 균일성을 얻기 위해 다양한 열처리 방법이 사용되고 있으며, 일반적인 열처리 방법으로는 conventional thermal annealing (CTA)과 rapid thermal annealing (RTA)이 많이 이용되고 있다. 본 실험에서는 microwave radiation에 의한 열처리로 소자의 특성을 개선시킬 수 있다는 사실을 확인하였고, 상대적으로 $100^{\circ}C$ 이하의 저온에서도 공정이 이루어지기 때문에 열에 의한 소자 특성의 열화를 억제할 수 있으며, 또한 짧은 처리 시간 및 공정의 단순화로 비용을 효과적으로 절감할 수 있다. 본 실험에서는 metal-oxide-silicon (MOS) 구조의 capacitor를 제작한 다음, 기존의 CTA나 RTA 처리가 아닌 microwave radiation을 실시하여 MOS capacitor의 전기적인 특성에 미치는 microwave radiation 효과를 평가하였다. 본 실험은 p-type Si 기판에 wet oxidation으로 300 nm 성장된 SiO2 산화막 위에 titanium/aluminium (Ti/Al) 금속 전극을 E-beam evaporator로 형성하여 capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 평가하였다. 그 결과, microwave 처리를 통해 flat band voltage와 hysteresis 등이 개선되는 것을 확인하였고, microwave radiation 파워와 처리 시간을 최적화하였다. 또한 일반적인 CTA 열처리 소자와 비교하여 유사한 전기적 특성을 확인하였다. 이와 같은 microwave radiation 처리는 매우 낮은 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA나 RTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 산화막과 실리콘 기판의 계면 특성 개선에 매우 효과적이라는 것을 나타낸다. 따라서, microwave radiation 처리는 향후 저온공정을 요구하는 nano-scale MOSFET의 제작 및 저온 공정이 필수적인 display 소자 제작의 해결책으로 기대한다.

• Journal of Power Electronics
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• v.19 no.1
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• pp.220-233
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• 2019

This work aims to study and analyze the various operating modes of universal power converter which is powered by solar and thermoelectric generators. The proposed converter is operated in a DC-DC (buck or boost mode) and DC-AC (single phase) inverter with high efficiency. DC power sources, such as solar photovoltaic (SPV) panels, thermoelectric generators (TEGs), and Li-ion battery, are selected as input to the proposed converter according to the nominal output voltage available/generated by these sources. The mode of selection and output power regulation are achieved via control of the metal-oxide semiconductor field-effect transistor (MOSFET) switches in the converter through the modified stepped perturb and observe (MSPO) algorithm. The MSPO duty cycle control algorithm effectively converts the unregulated DC power from the SPV/TEG into regulated DC for storing energy in a Li-ion battery or directly driving a DC load. In this work, the proposed power sources and converter are mathematically modelled using the Scilab-Xcos Simulink tool. The hardware prototype is designed for 200 W rating with a dsPIC30F4011 digital controller. The various output parameters, such as voltage ripple, current ripple, switching losses, and converter efficiency, are analyzed, and the proposed converter with a control circuit operates the converter closely at 97% efficiency.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.