• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.200-203
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• 2007

Devices of junction barrier schottky(JBS) structure using 4H-SiC substrates with wide energy band gaps was designed and fabricated. As a measurement results, the device of reverse I-V characteristics was shown as more than 1000 V, its design optimum length of p-grid was $3{\mu}m$ space. In this paper, I-V characteristics was modeled by using of device fabricated process conditions parameters and it was extracted that the I-V property parameters, and it was compared and analyzed with between device parameters and model parameters.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.157-157
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• 2011

박막형태로 제작이 가능한 비정질 실리콘은 결정질 실리콘에 비하여 AM-1 (Air Mass 1:100mW/cm2)조건하에서 10-3 S/cm 정도의 높은 광전기전도도와 가시광선 영역($4000{\sim}7000{\AA}$)에서 약 10배의 높은 광흡수계수를 가지며, $300^{\circ}C$ 이하의 낮은 기판온도에서 다양한 기판위에 대면적으로 제작이 가능할 뿐만 아니라 제작공정이 단순하여 제작비용이 저렴하다는 이점이 있다. 본 실험에서 제작된 모든 박막은 PECVD로 증착하였으며 구조는 p-i-n superstrate형 구조를 사용하였고, 각 박막의 두께는 p-a-Si:H/i-a-SiGe:H/n-a-Si:H ($300{\AA}/2000{\AA}/600{\AA}$)으로 고정하였다. a-Si:H (hydrogenated amorphous silicon) 태양전지의 광 흡수층인 i-layer에서의 germane 가스 유량 변화(0, 20, 40. 60, 80, 100 sccm)에 대한 흡수율의 차이를 UV/Vis/Nir spectrophotometer (ultraviolet/visible/near infrared spectrophotometer)를 통해 확인하고, 그에 따른 a-Si:H 박막 태양전지를 제작하여 solar simulator를 사용하여 AM 1.5 G의 환경 조건에서 태양전지 특성을 평가하였다. 그 결과 germane 가스 유량이 증가함에 따라 파장에 대한 absorptance (a.u.)값이 증가함을 알 수 있었으며, 흡수되는 파장영역의 범위가 장파장으로 확대됨을 확인할 수 있었다. 또한 germane 가스 유량이 60 sccm 일때 a-SiGe:H 박막 태양전지 변환효율이 3.80%로 최대값을 가졌다. 실험에서 germane 가스 유량이 증가할수록 흡수율이 높아져 태양전지특성이 향상될 거라 예상 했지만, 100 sccm보다 60 sccm일 때가 단락전류밀도 값과 변환효율이 높다는 것을 확인할 수 있었다. 이는 각 layer사이에 계면상의 문제가 있을 거라 예상되며 직렬저항측정을 통해 확인할 수 있다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.910-917
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• 2009

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2002.04b
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• pp.11-11
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• 2002

Plastic deformation was observed by TEM around the intragranular SiC particles in the $Al_2O_3$ matrix for $Al_2O_3/SiC$ nanocomposite system. The dislocations are generated at selected planes and there is a tendency for the dislocations to form a subgrain boundary structure with low-angel grain boundaries and networks. In this study, dislocation generated in the $Al_2O_3$ matrix during cooling down from sintering temperatures by the highly localized thermal stresses within and/or around SiC particles caused from the thermal expansion mismatch between $Al_2O_3$ matrix and SiC particle was observed. In monolithic $Al_2O_3$ and $Al_2O_3/SiC$ microcomposite system. These phenomena is closely related to the plastic relaxation of the elastic stress and strain energy associated with both thermal misfitting inclusions and creep behaviors. The plastic relaxation behavior was explained by combination of yield stress and internal stress.

• Korean Journal of Materials Research
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• v.21 no.12
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• pp.666-672
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• 2011

The a-Si:H/c-Si hetero-junction (HJ) solar cells have a variety of advantages in efficiency and fabrication processes. It has already demonstrated about 23% in R&D scale and more than 20% in commercial production. In order to further reduce the fabrication cost of HJ solar cells, fabrication processes should be simplified more than conventional methods which accompany separate processes of front and rear sides of the cells. In this study, we propose a simultaneous deposition of intrinsic thin a-Si:H layers on both sides of a wafer by dual hot wire CVD (HWVCD). In this system, wafers are located between tantalum wires, and a-Si:H layers are simultaneously deposited on both sides of the wafer. By using this scheme, we can reduce the process steps and time and improve the efficiency of HJ solar cells by removing surface contamination of the wafers. We achieved about 16% efficiency in HJ solar cells incorporating intrinsic a-Si:H buffers by dual HWCVD and p/n layers by PECVD.

• Progress in Superconductivity and Cryogenics
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• v.17 no.3
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• pp.1-4
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• 2015

Production of $MgB_2$ film on metallic Hastelloy with SiC as the buffer layer was achieved by means of hybrid physical-chemical vapor deposition technique, whereas SiC buffer layers with varied thickness of 170 and 250 nm were fabricated inside a pulsed laser deposition chamber. Superconducting transition temperature and critical current density were verified by transport and magnetic measurement, respectively. With SiC buffer layer, the reduced delaminated area at the interface of $MgB_2$-Hastelloy and the slightly increased $T_c$ of $MgB_2$ tapes were clearly noticed. It was found that the upper critical field, the irreversibility field and the critical current density were reduced when $MgB_2$ tapes were buffered with SiC buffer layer. Clarifying the mechanism of SiC buffer layer in $MgB_2$ tape in affecting the superconducting properties is considerably important for practical applications.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.123-126
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• 2022

We investigated deep levels in n-type 4H-SiC epitaxy layer of the Positive-Intrinsic-Negative diode and Schottky barrier diodes by using deep level transient spectroscopy. Despite the excellent performance of 4H-SiC, research on various deep level defects still requires a lot of research to improve device performance. In Positive-Intrinsic-Negative diode, two defects of 196K and 628K are observed more than Schottky barrier diode. This is related to the action of impurity atoms infiltrating or occupying the 4H-SiC lattice in the ion implantation process. The I-V characteristics of the Positive-Intrinsic-Negative diode shows about ~100 times lower the leakage current level than Schottky barrier diode due to the grid structures in Positive-Intrinsic-Negative. As a result of comparing the capacitance of devices diode and Schottky barrier diode devices, it can be seen that the capacitance value lowered if it exists the P implantation regions from C-V characteristics.

• Journal of the Korean Ceramic Society
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• v.37 no.7
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• pp.665-672
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• 2000

The ferroelectric YMnO3 thin films were prepared by MOD(metal-organic decomposition) method with Y- and Mn-acetylacetonate as starting materials. Thin films were grown on various substrates by spin-coating technique. The crystalline phases of the thin films were identified by X-ray diffractometer as a function of heat-treatment temperature, pH of coating solution and substrate. In addition, the effect of Mn/Y molar ratio(0.8~1.2) on the formation of hexagonal-YMnO3 phase was investigated. In forming highly c-axisoriented hexagonal-YMnO3 single phase, the Pt coated Si substrate was more effective than the bare Si substrate, and the optimum heat-treatment condition was at 82$0^{\circ}C$ for 30 min. Higher Mn/Y molar ratio within 0.8~1.2 and pH of YMnO3 precursor solution within 0.5~2.5 favored formation of ferroelectric hexagonal phase rather than orthorhombic phase. Leakage current density of the hexagonal-YMnO3 thin film formed on Pt(111)/TiO2/SiO2/Si substrate was low enough as 0.4~4.0$\times$10-8(A/$\textrm{cm}^2$) at 5 V and its remanent polarization(Pr), calculated from the P-E hysteresis loop, was 3 nC/$\textrm{cm}^2$.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.29-33
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• 2003

Material and electrical properties of copper-based ohmic contacts on n-type 4H-SiC were investigated for the effects of the post-annealing and the metal covering conditions. The ohmic contacts were prepared by sequential sputtering of Cu and Si layers on SiC substrate. The post-annealing treatment was performed using RTP (rapid thermal process) in vacuum and reduction ambient. The specific contact resistivity ($p_{c}$), sheet resistance ($R_{s}$), contact resistance ($R_{c}$), transfer length ($L_{T}$), were calculated from resistance (RT) versus contact spacing (d) measurements obtained from TLM (transmission line method) structure. The best result of the specific contact resistivity was obtained for the sample annealed in the reduction ambient as $p_{c}= 1.0 \times 10^{-6}\Omega \textrm{cm}^2$. The material properties of the copper contacts were also examined by using XRD. The results showed that copper silicide was formed on SiC as a result of intermixing Cu and Si layer.

• Journal of the Korean Physical Society
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• v.73 no.9
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• pp.1356-1361
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• 2018

Replacing conventional Si diodes with SiC diodes in Si insulated gate bipolar transistor (IGBT) modules is advantageous as it can reduce power losses significantly. Also, the fast switching nature of the SiC diode will allow Si IGBTs to operate at their full high-switching-speed potential, which at present conventional Si diodes cannot do. In this work, the electrical test results for Si-IGBT/4HSiC-Schottky hybrid substrates (hybrid SiC substrates) are presented. These substrates are built for two voltage ratings, 1.7 kV and 3.3 kV. Comparisons of the 1.7 kV and the 3.3 kV Si-IGBT/Si-diode substrates (Si substrates) at room temperature ($20^{\circ}C$, RT) and high temperature ($H125^{\circ}C$, HT) have shown that the switching losses in hybrid SiC substrates are miniscule as compared to those in Si substrates but necessary steps are required to mitigate the ringing observed in the current waveforms. Also, the effect of design variations on the electrical performance of 1.7 kV, 50 A diodes is reported here. These variations are made in the active and termination regions of the device.