• 한국전기전자재료학회논문지
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• 제13권7호
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• pp.568-574
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• 2000

We have been optimized tungsten(W) plug CMP(chemical mechanical polishing) characteristics using two different kinds of component of slurry and two different kinds of pad which have different hardness. The comparison of oxide film roughness on around W plug after polishing has been carried out. And W plug recess for consumable sets and dishing effect at dense area according to the rate of over-polishing has been investigated. Also the analysis of residue on surface after cleaning have been performed. As a experimental result we have concluded that the consumable set of slurry A and hard pad was good for W plug CMP process. After decreasing the rate of chemical reaction of silica slurry and adding two step buffering we could reduce the expanding of W plug void however we are still recognizing to need a more development for those kinds of CMP consumables.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.167-172
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• 2006

Submicron colloidal silica coated with ceria were prepared by mixing of silica and nano ceria particles and modified by hydrothermal reaction. The polishing efficiency of the ceria coated silica slurry was tested over oxide film on silicon wafer. By changing the polishing pressure in the range of $140{\sim}420g/cm^2$ with the ceria coated silica slurries in $100{\sim}300nm$, rates, WIWNU and friction force were measured. The removal rate was in the order of 200, 100, and 300 nm size silica coated with ceria. It was known that the smaller particle size gives the higher removal rate with higher contact area in Cu slurry. In the case of oxide film, the indentation volume as well as contact area gives effect on the removal rate depending on the size of abrasives. The indentation volume increase with the size of abrasive particles, which results to higher removal rate. The highest removal rate in 200 nm silica core coated with ceria is discussed as proper combination of indentation and contact area effect.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.812-816
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• 2000

It is very important to understand the correlation of between inter dielectric(ILD) CMP process and various facility factors supplied to equipment to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD-CMP process was studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyze various facilities supplied at supply system. With facility shortage of D.I water(DIW) pressure, we introduced an adding purified $N_2$(P$N_2$)gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and P$N_2$gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and P$N_2$gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.31-34
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• 2000

It is very important to understand the correlation of between inter layer dielectric(ILD) CMP process and various facility factors supplied to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD CMP process were studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyzed various facilities supplied at supply system. With facility shortage of D.I. water(DIW) pressure, we introduced an adding purified $N_2(PN_2)$ gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and PN2 gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and PN2 gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.525-526
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• 2007

Over-polishing is required to completely remove the material of top surface across whole wafer, in spite of a local dishing problem. This paper introduces the two-step CMP process using protective layer and high selectivity slurry, to reduce dishing amount and variation. The 30nm thick protective oxide layer was deposited on the pattern, and then polished with low selectivity slurry to partially remove the projected area while suppressing the removal rate of the recessed area. After the first step CMP process, high selectivity slurry was used to minimize the dishing amount and variation in pattern structure. Experimental result shows that two-step CMP process can be successfully applicable to reduce the dishing defect generated in over-polishing.

• Korea-Australia Rheology Journal
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• 제14권2호
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• pp.63-70
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• 2002

Chemical mechanical planarization (CMP) is the polishing process enabled by both chemical and mechanical actions. CMP is used in the fabrication process of the integrated circuits to achieve adequate planarity necessary for stringent photolithography depth of focus requirements. And recently copper is preferred in the metallization process because of its low resistivity. We have studied the effects of chemical reaction on the polishing rate and surface planarity in copper CMP by means of numerical simulation solving Navier-Stokes equation and copper diffusion equation. We have performed pore-scale simulation and integrated the results over all the pores underneath the wafer surface to calculate the macroscopic material removal rate. The mechanical abrasion effect was not included in our study and we concentrated our focus on the transport phenomena occurring in a single pore. We have observed the effects of several parameters such as concentration of chemical additives, relative velocity of the wafer, slurry film thickness or ash)tract ratio of the pore on the copper removal rate and the surface planarity. We observed that when the chemical reaction was rate-limiting step, the results of simulation matched well with the experimental data.

• Tribology and Lubricants
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• 제32권2호
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• pp.61-66
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• 2016

Total thickness variation (TTV), BOW, and surface roughness are essential characteristics for high quality sapphire substrates. Many researchers have attempted to increase removal rate by controlling the key process parameters like pressure and velocity owing to the high cost of consumables in sapphire chemical mechanical polishing (CMP). In case of the pressure approach, increased pressure owing to higher deviation of pressure over the wafer leads to significant degradation of the TTV. In this study, the authors focused on reducing TTV under the high-pressure conditions. When the production equipment polishes multiple wafers attached on a carrier, higher loads seem to be concentrated around the leading edge of the head; this occurs because of frictional force generated by the combination of table rotation and the height of the gimbal of the polishing head. We believe the skewed pressure distribution during polishing to be the main reason of within-wafer non-uniformity (WIWNU). The insertion of a hub ring between the polishing head and substrate carrier helped reduce the pressure deviation. Adjusting the location of the hub ring enables tuning of the pressure distribution. The results indicated that the position of the hub ring strongly affected the removal profile, which confirmed that the position of the hub ring changes the pressure distribution. Furthermore, we analyzed the deformation of the head via finite element method (FEM) to verify the pressure non-uniformity over the contact area Based on experiment and FEM results, we determined the optimal position of hub ring for achieving uniform polishing of the substrate.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.55-56
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• 2006

This research was carried out to observe the structure and characteristics of SUBA pad for silicon wafer polishing. As the diamond size is smaller and shape is rounder, the pad cut rate becomes smaller. From the experimental results, we suggests that the diamond grade should be over 680 when the diamond mesh is between #100 and #170 for SUBA pad.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 춘계학술대회 논문집
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• pp.854-857
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• 2000

Chemical Mechanical Polishing(CMP) has been accepted as one of the essential processes for VLSI fabrication. However, as the polishing process continues, pad pores get to be glazed by polishing residues, which hinder the supply of new slurry. This defect makes removal rate decrease with a number of polished wafer and the desired within-chip planarity, within wafer and wafer-to-wafer nonuniformity are unable to be achieved. So, pad conditioning is essential to overcome this defect. The eletroplated diamond grit disk is used as the conventional conditioner, And alumina long fiber, the .jet power of high pressure deionized water and vacuum compression are under investigation. But, these methods have the defects like scratches on wafer surface by out of diamond grits, subsidences of pad pores by over-conditioning, and the limits of conditioning effect. To improve these conditioning methods. this paper presents the Characteristics of Ultrasonic conditioning aided by cavitation.

• 대한기계학회논문집A
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• 제37권3호
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• pp.313-318
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• 2013

전자기력을 이용한 자기연마 공정은 전통적 가공방식으로 버를 제거하기 힘든 비자성체의 소재 및 마이크로 형상의 가진 제품에 활용될 수 있는 새로운 정밀 디버링 방식이다. 그러나 이러한 자기연마법은 자기연마입자를 이용한 기계적 절삭력을 이용하고 있기 때문에 마이크로 단위의 구조물의 형상을 변형시킬 가능성이 높다. 따라서 본 연구에서는 탄소나노튜브-코발트 금속복합체를 이용한 전해-자기복합가공을 STS316 소재의 미세 그루브의 마이크로 디버링공정에 적용하고 그 특성을 분석하였다. 그 결과 자기연마공정을 적용한 공정에서는 공정 후 그루브에 생성된 버는 효율적으로 제거되었으나 그루브 끝단의 형상변화가 두드러지게 관찰되었다. 반면 전해-자기복합가공을 이용한 경우에는 재료제거율이 낮아 그루브 끝단의 형상변화 없이 디버링 공정이 진행됨을 확인하였다.