• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.50-59
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• 2016

This work shows that the design and test results of a power amplifier(PA) with broadband and high linearity for 4G applications in $0.11{\mu}m$ CMOS process. A 1:2-transformer is designed for load impedance matching of PA and a inter-stage matching is implemented for a linearity. A designed PA achieves more than 27.3 dBm of linear output power and 26.1 % of power-added efficiency(PAE) under an adjacent channel leakage ratio(ACLR) of -30 dBc for a LTE 16-QAM 10 MHz signal with a carrier frequency range of 1.8 to 2.3 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.335-344
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• 2004

A low phase noise EQM(Engineering Qualified Model) LO(Local Oscillator) has been developed for Ka-band satellite transponder. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is also designed using a high impedance inverter coupled with dielectric resonator to improve the phase noise performances out of the loop bandwidth. The mechanical analysis fur housing and the thermal analysis fur circuit board are achieved. This EQM LO is applied to Ka-band satellite transponder of EQM level after environmental experiments for space application. The LO has the harmonic suppression characteristics above 52 ㏈c and requires low power consumption under 1.3 watts. The phase noise characteristics are exhibited as -101.33 ㏈c/㎐ at 10 ㎑ offset frequency and -114.33 ㏈c/㎐ at 100 ㎑ offset frequency, with the output power of 14.0 ㏈m${\pm}$0.17 ㏈ over the temperature range of -15∼＋65$^{\circ}C$.

• Journal of IKEEE
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• v.24 no.1
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• pp.368-371
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• 2020

In this paper, we propose a linear tapered slot rectifying antenna for a portable UHF-band RFID system. Since the proposed rectifying antenna does not use a dielectric substrate, the planar antenna is implemented with a thin metal thickness. The rectifier circuit converts input RF power into output DC voltage using a voltage doubler circuit based on two anti-parallel schottky diodes. The rectifying antenna is integrated by the voltage doubler circuit into a linear tapered slot antenna. For conjugate impedance matching of the rectifying circuit and the linear tapered slot antenna, the source-pull method was utilized by adjusting the angle of the tapered slot and the length of the antenna feed line. The proposed antenna prototype has been verified with the electrical and radiation characteristics through RF-DC conversion and far-field radiation test in open space measurement environment. Finally, the proposed antenna is realized to 0.23-wavelength (75 mm) and 0.18-wavelength (60 mm) at 915 MHz center frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.357-360
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.54-61
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• 2007

A variable gain low noise amplifier (VG-LNA) implemented in TSMC 0.18 um process is presented. This VG-LNA is designed of two stage amplifier, and its gain is controlled by the shunt feedback loop composed of a gain control transistor (GCT) and a coupling capacitor in second stage. The channel resistance of GCT in the shunt feedback loop influences the input and output stages of a second stage by the Miller effect. Total gain of the proposed VG-LNA is changed by two factors, the load impedance reduction and the interstage mismatch by controlling the channel resistance of the GCT. Consequently, by adding a shunt feedback with a gain control transistor, this proposed VG-LNA achieves both wide gain tuning range of 37 dB and continuous gain control simultaneously.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.9
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• pp.55-59
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• 2008

In this paper, the linearity of Doherty amplifier has been improved by applying a compact slow-wave microstrip branch-line coupler on the output of Doherty amplifier. The proposed branch coupler has four microstrip high-low impedance resonant cells periodically placed inside the branch-line coupler to result in high slow-wave effect. The new coupler not only effectively reduces the occupied area to 30% of the conventional branch-line coupler at 1.8GHz, but also has high second harmonic suppression performance. We obtained the 3rd-order intermodulation distortion ($IMD_3$) of -31.16 dBc for CDMA applications with that of maintaining the constant power added efficiency (PAE). The IMD3 performance is improved as much as -7 dBc compared with a Doherty amplifier.

• Journal of Communications and Networks
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• v.15 no.6
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• pp.559-568
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• 2013

We report on the first error-free terahertz (THz) wireless communication at 0.310 THz for data rates up to 8.2 Gbps using a 18-GHz-bandwidth GaAs/AlGaAs field-effect transistor as a detector. This result demonstrates that low-cost commercially-available plasma-wave transistors whose cut-off frequency is far below THz frequencies can be employed in THz communication. Wireless communication over 50 cm is presented at 1.4 Gbps using a uni-travelling-carrier photodiode as a source. Transistor integration is detailed, as it is essential to avoid any deleterious signals that would prevent successful communication. We observed an improvement of the bit error rate with increasing input THz power, followed by a degradation at high input power. Such a degradation appears at lower powers if the photodiode bias is smaller. Higher-data-rate communication is demonstrated using a frequency-multiplied source thanks to higher output power. Bit-error-rate measurements at data rates up to 10 Gbps are performed for different input THz powers. As expected, bit error rates degrade as data rate increases. However, degraded communication is observed at some specific data rates. This effect is probably due to deleterious cavity effects and/or impedance mismatches. Using such a system, realtime uncompressed high-definition video signal is successfully and robustly transmitted.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.768-773
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• 2012

A branch-line hybrid using microstrip artificial transmission lines(ATLs) with slotted-triangular patches is proposed. The proposed artificial transmission line is compact in structure as well as easy to adjust the characteristic impedance and electrical length of equivalent transmission line by changing the slot's parameters; hence, it is useful for miniaturizing conventional transmission lines. The designed branch-line hybrid, because of the use of the right angled isosceles triangular shaped artificial transmission lines as building blocks, has no useless empty space, and hence optimally miniaturized. A fabricated 3 dB branch-line hybrid shows the coupling variation of ${\pm}0.5$ dB and the phase difference between two output ports of $91^{\circ}{\pm}4^{\circ}$ within 15 % bandwidth at 2.45 GHz center frequency. The size of proposed branch-line hybrid is only 38% of the conventional branch-line hybrid.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.1
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• pp.35-44
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• 1998

In this paper, input LC filter design of diode rectifiers considering filter V A rating reduction has been propoesd. It consisted of an input LC parallel resonent tank whose inductor and capacitor values are se$.$ lected so that the input filter presents an infinite impedance to harmonic input ac current component. The operation of proposed input filter has been analyzed in detail under steady state conditions. Performance evaluation and related design data have been provided on Per Unit basis for the proper implementation of diode rectification system. Finally, Detailed input and output current analysis has shown that the proposed input filter yield high quality input ac current waveforms, in particular, high input power factor values and more reliabilty which reducing the V A rating of passive components as compared to the standard type LC filter.filter.