• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.27-37
• /
• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.111-117
• /
• 2006

Reconfigurable CMOS low-noise amplifier (LAN) has been developed for multi-mode/multi-band wireless receiver. By employing common-gate input stage, the performance can be optimized for multiple operation bands by simply controlling the output load impedance. Although the conventional common-gate LAN has larger than 3dB noise figure (NF), the newly developed negative feedback scheme enables the common-gate input LNA to have less than 2dB NF. To have optimum linearity performance of wireless receiver, the gain of the LNA can be controlled. The LNA implemented in a 0.13mm CMOS technology shows $19{\sim}20dB$ voltage gain, $1.7{\sim}2.0dB$ NF, -2dBm iIP3 at $1.8{\sim}2.5GHz$ frequency range. The LNA dissipates 7mW from a 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.8
• /
• pp.42-50
• /
• 2007

This paper presents design methods for dual-frequency(2.4/5.8GHz) active receiving antennas. The proposed active receiving antennas are designed to interconnect the output port of a wideband antenna to the input port of an active device of High Electron Mobility Transistor directly and to receive RF signals of 2.4GHz and 5.2GHz simultaneously where the impedance matching conditions are optimized by adjusting the length of $1/20{\lambda}_0$(@5.8GHz) CPW transmission line in the planar antenna The bandwidth of implemented dual-frequency active receiving antennas is measured in the range of 2.0GHz to 3.1GHz and 5.25GHz to 5.9GHz. Gains are measured of 17.0dB at 2.4GHz and 15.0dB at 5.2GHz. The measured noise figure is 1.5dB at operating frequencies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.4
• /
• pp.290-298
• /
• 2018

Herein, an S-band internally-matched power amplifier that shows a power capability of 300 W in a Long Term Evolution(LTE) band 7 is designed and fabricated using a CGHV40320D GaN HEMT from Wolfspeed. Based on the nonlinear model, the optimum source and load impedance are extracted from the source-pull and load-pull simulations at the fundamental and harmonic frequencies, and the harmonic impedance tuning circuits are implemented inside a ceramic package. The internally matched power amplifier, which is fabricated using a thin-film substrate with a high relative permittivity of 40 and an RF35TC PCB substrate, is measured at the pulsed condition with a pulse period of 1 ms and a duty cycle of 10%. The measured results show a maximum output power of 257~323 W, a drain efficiency of 64~71%, and a power gain of 11.5~14.0 dB at 2.62~2.69 GHz. The LTE-based measurement shows a drain efficiency of 42~49% and an ACLR of less than -30 dBc(excluding 2.62 GHz) at an average power of 79 W.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.7 s.361
• /
• pp.9-15
• /
• 2007

In this paper, we present the design of Schottky diodes and voltage multiplier for UHF-band passive RFID applications. The Schottky diodes were fabricated using Titanium (Ti/Al/Ta/Al)-Silicon (n-type) junction in $0.35\;{\mu}m$ CMOS process. The Schottky diode having $4{\times}10{\times}10\;{\mu}m^{2}$ contact area showed a turn-on voltage of about 150 mV for the forward diode current of $20\;{\mu}A$. The breakdown voltage is about -9 V, which provides sufficient peak inverse voltage necessary for the voltage multiplier in the RFID tag chip. The effect of the size of Schottky diode on the turn-on voltage and the input impedance at 900 MHz was investigated using small-signal equivalent model. Also, the effect or qualify factor of the diode on the input voltage to the tag chip is examined, which indicates that high qualify factor Schottky diode is desirable to minimize loss. The fabricated voltage multiplier resulted in a output voltage of more than 1.3 V for the input RF signal of 200mV, which is suitable for long-range RFID applications.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.7
• /
• pp.1639-1645
• /
• 2015

In UHD high-speed video transmission system, when a signal within certain frequency region coincides electrically and structurally, the system becomes unstable because the energy is concentrated, and signal flux is interfered and distorted. For the instability, power integrity analysis should be conducted. To remove the signal distortion for MLB, using a high-frequency design technique for EMI phenomenon, EMI which radiates electromagnetic energy fluxed into power layer was analyzed considering system stabilization. In this paper, we proposed an adaptive MLB design method which minimizes high-frequency noise in MLB structure, enhances signal integrity and power integrity, and suppresses EMI. The characteristic impedance for multi-layer circuit board proposed in this study were High-Speed Video Differential Signaling(HSVDS) line width w = 0.203, line gap d = 0.203, beta layer height h = 0.145, line thickness t = 0.0175, dielectric constant ε_r = 4.3, and characteristic impedance Zdiff = 100.186Ω. When high-speed video differential signal interface board was tested with optimized parameters, the magnitude of Eye diagram output was 672mV, jittering was 6.593ps, transmission frequency was 1.322GHz, signal to noise was 29.62dB showing transmission quality improvement of 10dB compared to previous system.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.3
• /
• pp.699-706
• /
• 2010

We have studied to obtain the slanted finger interdigital(SFIT) type filter was formed on the Langasite substrate and was evaporated two IDT electrode by Aluminum-Copper alloy respectively. We can fabricate that the block weighted type IDT as an input transducer of the filter and the withdrawal weighted type IDT as an output transducer of the filter from the results of our computer-simulation. Also, we have performed to obtain the properly design conditions about phase shift conditions of the SPIT type filter. We have employed that the number of pairs of the input and output IDT are 50 pairs and the thickness and the width of reflectors are $5000\;{\AA}$ and $3.6{\mu}m$ respectively. At the first sample, we have employed that the distance from the hot electrode to the reflectors is $2.4{\mu}m$ distance from the ground electrode to the reflectors is $1.8{\mu}m$ and the distance from the hot electrode to the ground is $1.5{\mu}m$ respectively. At the other sample, we have also employed that the distance from the hot electrode to the reflectors and the distance from the ground electrode to the reflectors are $2.4{\mu}m$. Frequency response of the fabricated SAW filter has the property that the center frequency is about 190MHz and bandwidth at the 3dB is probably 7.3 MHz. And we could obtain that return is less than -20dB, ripple characteristics is probably 3dB and triple transit echo(TTE) is less than -22dB after when we have matched impedance.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.40-48
• /
• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.4
• /
• pp.62-68
• /
• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.10
• /
• pp.892-899
• /
• 2016

In this paper, an X-band 50 W internally matched power amplifier is designed and fabricated using an $80{\times}150{\mu}m$ GaN HEMT that is developed by the $0.25{\mu}m$ GaN HEMT process of ETRI. The optimum source and load impedances are experimentally extracted from the loadpull measurement using impedance-transform-prematching circuits, and the transistor performance is predicted. The power performance of the internally matched power amplifier, whose matching circuits are fabricated on a substrate with ${\varepsilon}_r$ of 10.2, is measured under the pulsed mode of $100{\mu}s$ pulse period and 10 % duty cycle, and the best output power of 47.46 dBm(55.5 W) and the power-added efficiency of 46.6 % are obtained at 9.2 GHz. The output power of 47~47.46 dBm(50~55.7 W) is measured in 9.0~9.5 GHz, and the power-added efficiency is measured to be greater than 43 % in 9.0~9.3 GHz and above 36 % in 9.4~9.5 GHz.