• 한국재료학회지
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• 제16권5호
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• pp.302-307
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• 2006

The formation and processing of organic insulators on the device performance have been studied in the fabrication of organic thin film transistors (OTFTs). The series of polyvinyls, poly-4-vinyl phenol(PVP) and polyvinyltoluene (PVT), were used as solutes and propylene glycol monomethyl ether acetate(PGMEA) as a solvent in the formation of organic insulators. The cross-linking of organic insulators was also attempted by adding the thermosetting material, poly (melamine-co-formaldehyde) as a hardener in the compound. The electrical characteristics measured in the metal-insulator-metal (MIM) structures showed that insulating properties of PVP layers were generally superior to those of PVT layers. Among the layers of PVP series: PVP(10 wt%) copolymer, 5 wt% cross-linked PVP(10 wt%), PVP(20 wt%) copolymer, 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%), the 10 wt% cross-linked PVP(20 wt%) layer showed the lowest leakage current characteristics. Finally, inverted staggered OTFTs using the PVP(20 wt%) copolymer, 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%) as gate insulators were fabricated on the polyether sulphone (PES) substrates. In our experiments, we could obtain the maximum field effect mobility of 0.31 $cm^2/Vs$ in the device from 5 wt% cross-linked PVP(20 wt%) and the highest on/off current ratio of $1.92{\times}10^5$ in the device from 10 wt% cross-linked PVP(20 wt%).

• 청정기술
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• 제30권1호
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• pp.13-22
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• 2024

본 연구에서는 6,13-Bis(triisopropylsilylethynyl)pentacene(TP):2-Decyl-7-phenyl[1]benzothieno[3,2-b][1]benzothiophene(BT):Poly styrene (PS) 블랜딩 thin film transistor (TFT)를 제작 광 흡수 센서로의 활용에 대해 탐구한다. BT의 혼합으로 인해 off current 감소와 on/off ratio 향상을 동시에 달성하였다. 특히, TP:BT:PS (1:0.25:1 w/w) 샘플은 우수한 광 흡수 특성을 보여주었고, 이를 통해 높은 성능의 광 흡수 장치 제작이 가능함을 입증했다. 다양한 혼합 비율의 결정 구조와 전기적 특성에 대한 분석을 통해 TP:BT:PS (1:0.25:1 w/w) 샘플이 최적임을 확인하였다. 이 결과는 광 흡수 장치의 발전 뿐만 아니라 혼합 organic semiconductor (OSC)의 광전자 시스템 개발에 긍정적인 기대효과를 미칠 수 있을 것이며, 이를 통해 단일 OSC 사용의 제약을 극복하고, 미세 조정된 광학 응답을 갖춘 고성능 OSC TFT를 제작하여 의료 전자소자, 산업용 전자소자 등에 응용할 수 있을 것으로 기대된다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.1.1-1.1
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• 2011

Printed electronics based on the direct writing of solution processable functional materials have been of paramount interest and importance. In this talk, the synthesis of printable inorganic functional materials (conductors and semiconductors) for thin-film transistors (TFTs) and photovoltaic devices, device fabrication based on a printing technique, and specific characteristics of devices are presented. For printable conductor materials, Ag ink is designed to achieve the long-term dispersion stability and good adhesion property on a glass substrate, and Cu ink is sophisticatedly formulated to endow the oxidation stability in air and even aqueous solvent system. The both inks were successfully printed onto either polymer or glass substrate, exhibiting the superior conductivity comparable to that of bulk one. In addition, the organic thin-film transistor based on the printed metal source/drain electrode exhibits the electrical performance comparable to that of a transistor based on a vacuum deposited Au electrode. For printable amorphous oxide semiconductors (AOSs), I introduce the noble ways to resolve the critical problems, a high processing temperature above $400^{\circ}C$ and low mobility of AOSs annealed at a low temperature below $400^{\circ}C$. The dependency of TFT performances on the chemical structure of AOSs is compared and contrasted to clarify which factor should be considered to realize the low temperature annealed, high performance AOSs. For photovoltaic application, CI(G)S nanoparticle ink for solution processable high performance solar cells is presented. By overcoming the critical drawbacks of conventional solution processed CI(G)S absorber layers, the device quality dense CI(G)S layer is obtained, affording 7.3% efficiency CI(G)S photovoltaic device.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.1277-1280
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• 2005

A high-aspect-ratio and high-resolution stainless steel shadow mask for organic thin-film transistors (OTFTs) circuit has been fabricated by a new method which combines photochemical machining, micro-electrical discharge machining (micro-EDM), and electrochemical etching (ECE). First, connection lines and source-drain holes are roughly machined by photochemical etching, and then the part of source and drain holes is finished by the combination of micro-EDM and ECE processes. Using this method a $100\;\mu{m}$ thick stainless steel (AISI 304) shadow mask for inverter can be fabricated with the channel length of $30\;\mu{m}\;and\;10\;\mu{m}\;respectively.\;The\;width\;of\;connection line\;is\;150\;\mu{m}$. The aspect ratio of the wall is about 5 and 15, respectively. Metal lines and source-drain electrodes of OTFTs were successfully deposited through the fabricated shadow mask.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1336_1337
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• 2009

본 논문에서는 유기 박막 트랜지스터의 전극을 잉크젯 프린팅과 스크린 프린팅 방법을 이용하여 유기 박막 트랜지스터를 제작하였다. 전극으로 PEDOT:PSS와 Ag 잉크를 사용하였고, 게이트 절연막으로 polymethyl methacrylate (PMMA)와 poly(4-vinylphenol) (PVP)를 사용하였다. 유기물 활성층으로 pentacene을 진공 증착하였다. 잉크젯 프린팅 방법을 이용하여 제작한 유기 박막 트랜지스터는 전계이동도 (${\mu}_{FET}$) $0.068\;cm^2$/Vs, 문턱전압 ($V_{th}$) -15 V, 전류 점멸비 ($I_{on}/I_{off}$ current ratio) >$10^4$의 전기적 특성을 보였고, 스크린 인쇄 방법을 이용하여 제작한 유기 박막 트랜지스터는 전계이동도 (${\mu}_{FET}$) $0.016\;cm^2$/Vs, 문턱전압 ($V_{th}$) 6 V, 전류 점멸비 ($I_{on}/I_{off}$ current ratio) >$10^4$의 전기적 특성을 보였다. 이를 통하여 프린팅 방법을 이용한 유기 박막 트랜지스터 단일 소자 및 유기 전자 회로 제작의 가능성을 확인 하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1361-1363
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• 2005

In this paper, we report on the performance stability of solution processible OTFT devices with Au/Ti and ITO source-drain (S/D) electrodes. It appears that the contact resistance of the S/D electrode strongly affects the stability of OTFT devices. Interestingly, the devices with the Au/Ti electrode showed lower mobility than those with the ITO (S/D) devices. The field effect mobilities of the devices with the Au/Ti and ITO electrodes were 0.06, and $0.44cm^2/Vs$, respectively. However, the mobility of the device with the Au/Ti electrode was increased up to $0.26cm^2/Vs$ after 2 weeks, while the mobility of the device with ITO electrode was slightly decreased down to $0.41cm^2/Vs$. The experimental data show us that ITO could be used as the S/D electrode for low-cost OTFT devices.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1301-1305
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• 2005

The performance of OTFT with $PVP-TiO_2$ composite, as a gate insulator, is reported, including the effect of surfactant for synthesizing the composite material. According to our investigation results, it was one of critical issues to prevent the aggregation of $PVP-TiO_2$ particles during the synthesis process. From this point of view, $PVP-TiO_2$ particles were treated using Tween80, as a surfactant, and we could reduce the aggregated $PVP-TiO_2$ clusters. As a result, the OTFT with the composite insulator showed the threshold voltage of about -8.3 V and the subthreshold slope of about 1.5 V/decade, which are the optimized properties compared to those of OTFTs with bare PVP, in this study. It is thought that these characteristic improvements are originated from the increase in the dielectric constant of the PVP-based insulator by compositing with high-k particles.

• 전기학회논문지
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• 제61권6호
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• pp.817-820
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• 2012

We studied p-type capacitance characteristics of ZnO thin-film transistors (TFT's), grown by metal organic chemical vapor deposition (MOCVD). We compared two ZnO TFT's: one grown at $450^{\circ}C$ and the other grown at $350^{\circ}C$. ZnO grown at $450^{\circ}C$ showed smooth capacitance profile with electron density of $1.5{\times}10^{20}cm^{-3}$. In contrast, ZnO grown at $350^{\circ}C$ showed a capacitance jump when gate voltage was changed to negative voltages. Current-voltage characteristics measured in the two samples did not show much difference. We explain that the capacitance jump is related to p-type ZnO layer formed at the $SiO_2$ interface. Current-voltage and capacitance-voltage data support that p-type characteristics are observed only when background electron density is very low.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.287-287
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• 2010

We report a new direct patterning method, called liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sizes between tens of nanometers and tens of micron over large areas. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. This procedure can be adopted for automated direct printing machines that generate patterns of functional materials with a wide range of feature sizes on diverse substrates. Arrays of TIPS-PEN TFTs were fabricated on 4" polyethersulfone (PES) substrates by LB-nTM using PDMS molds. An inverted staggered structure was employed in the TFT device fabrication. A 150 nm-thick indium-tin oxide (ITO) gate electrode and a 200 nm-thick SiO2dielectric layer were formed on a PES substrate by sputter deposition. An array of TIPS-PEN patterns (thickness: 60 nm) as active channel layers was fabricated on the substrate by LB-nTM. The nominal channel length of the TIPS-PEN TFT was 10 mm, while the channel width was 135 mm. Finally, the source and drain electrodes of 200 nm-thick Ag were defined on the substrate by LB-nTM. The TIPS-PEN TFTs can endure strenuous bending and are also transparent in the visible range, and therefore potentially useful for flexible and invisible electronics.

• 대한전자공학회논문지SD
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• 제43권6호
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• pp.1-8
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• 2006

본 논문에서는 OTFT를 기반으로 하는 AMOLED 디스플레이 구현을 위해 두 개의 OTFT와 하나의 캐패시터 그리고 하나의 OLED로 구성된 화소 회로를 설계하였고 그 동작을 시뮬레이션을 통하여 분석하였다. 먼저, 화소 회로를 이론적으로 설계하였고, $32\times32$ AMOLED 패널을 제작하기 위한 화소의 Layout을 설계하고 TFT W/L과 저장 캐패시터의 용량을 설계하였다. 그리고 설계된 화소 회로의 전기적 특성을 분석하기 위해 HSPICE 시뮬레이션 하였다 시뮬레이션 결과 OTFT 기반의 AMOLED 구현 가능성을 확인하였다.