• JSTS:Journal of Semiconductor Technology and Science
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• 제5권3호
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• pp.168-172
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• 2005

In this paper, we present a new adaptive biasing scheme for CMOS op-amps. The designed circuit has been used in an Operational Transconductance Amplifier (OTA) with ${\pm}1$ V power supply, and it has improved the positive and negative slew rates from 2.92 V/msec to 1242 V/msec and from 1.56 V/msec to 133 V/msec respectively, while maintaining all the small-signal performance parameter values the same as that without adaptive biasing (as expected), however, there was a marginal decrease of the dynamic range. The most useful features of the proposed circuit are that it uses a very low number of components (thus not creating severe area penalty) and requires only 25 nW of extra stand-by power.

• 전자공학회논문지SC
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• 제43권5호
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• pp.28-35
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• 2006

본 논문은 회로 구성 블록으로 CMOS 연산 트랜스컨덕턴스 증폭기(OTA)를 사용한 새로운 3.3-1 V 동기식 buck DC/DC 컨버터를 제안한다. PWM 회로의 오차 증폭기 OTA는 온도 안정성 향상을 위해 보상되었다. 보상된 OTA 트랜스컨덕턴스 이득의 온도 계수는 $0-100^{\circ}C$ 범위에서 $150\;ppm/^{\circ}C$ 이하이다. $0.35{\mu}m$ 표준 CMOS 공정으로 HSPICE 시뮬레이션을 수행한 결과는 40-125 mA의 부하 전류 범위에서 제안된 컨버터의 효율이 80% 이상임을 보여준다. 이러한 결과는 제안된 컨버터가 전지로 동작되는 시스템에 이용하기에 적당함을 보여준다.

• Transactions on Electrical and Electronic Materials
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• 제15권3호
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• pp.149-154
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• 2014

A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. This idea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. The channel length of the source-side MOSFET is optimized, to give higher transconductance ($g_m$) and output resistance ($r_{out}$). The highest $g_m$ and $r_{out}$ of the SC structures are obtained by independently optimizing the channel length ratio of the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposed design methodology using a standard digital $0.18-{\mu}m$ CMOS technology was designed and fabricated, to provide better performance. Independently $g_m$ and $r_{out}$ optimized SC MOSFETs were used in the differential input and output stages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology was approximately 18 dB higher, than that of the conventional OPAMP.

• Journal of Semiconductor Engineering
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• 제2권1호
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• 대한전자공학회논문지SD
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• 제44권7호통권361호
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• pp.37-44
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• 2007

GSM 셀룰러폰을 위한 저전압 고선형 바이폴라 OTA와 이룡 이용한 IF bandpass filter(BPF)를 제안하였다. OTA는 저전압 선형 transconductor, translinear 전류이득 셀, 그리고 3개의 전류 미러로 구성 되어있다. BPF는 2개의 동일한 2차 BPF를 직렬 연결한 형태인데, 2차 BPF는 저항과 커패시터 그리고 2개의 OTA와 커패시터로 된 ground simulated inductor로 구성되어 있다. 8GHz bipolar transistor-array를 사용한 SPICE 시뮬레이션에서는 1mS의 transconductance의 OTA가 ${\pm}2%$ 이하의 선형 오차와 ${\pm}2\;V$에서 ${\pm}0.65\;V$이상의 선형범위를 가짐을 보여준다. transconductor의 온도계수는 $-90ppm/^{\circ}C$이하이다. BPF는 중심 주파수는 $85MHz\;Q$값은 80이 되도록 설계하였다. 중심주파수에서의 온도계수는 $-182ppm/^{\circ}C$이고, BPF의 소비전력은 128mW 이다.

• 전자공학회논문지
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• 제50권6호
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• pp.91-98
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• 2013

생체자기신호 측정을 위해 고인덕턴스 코일과 계측 증폭기를 내장한 자기센서칩을 $0.18{\mu}m$ CMOS공정으로 제작하였다. 생체자기신호를 측정하기 적합한 감도와 대역폭을 가지는 고인덕턴스 코일센서를 전자기장 시뮬레이션 프로그램으로 설계하였으며, 온칩에 구현하기 위해 트렌스컨덕턴스 감쇄방법 적용한 low gm OTA를 구현하였다. 자기센서칩의 출력신호 감도는 $3.25fT/{\mu}V$이며, output reference noise는 21.1fT/${\surd}$Hz이다. 계측 증폭기부분은 current feedback 기반으로 설계되었으며, 자기 신호 잡음을 줄이기 위해서 0.5~5kHz의 대역의 BPF를 설계하였다. MPW칩 테스트에서 common mode rejection ratio(CMRR)는 117.5dB로 측정하였으며, input reference noise가 $0.87{\mu}V$ 이하로 유지되도록 설계하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.770-773
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• 2002

Two sinusoidal voltage-controlled oscillators using linear operational transconductance amplifiers are presented in this paper: One is based on the positive-feedback bandpass oscillator model and the other on the negative-feedback Colpitts model. The bandpass VCO consists of a noninverting amplifier and a current-controlled LC-tuned circuit which is realized by two linear OTA's and two grounded capacitors, while the Colpitts VCO consists of an inverting amplifier and a current-controlled LC-tuned circuit realized by three linear OTA's and three grounded capacitors. Prototype circuits have been built with discrete components. The experimental results have shown that the Colpitts VCO has a linearity error of less than 5 percent, a temperature coefficient of less than rm 100 ppm/$^{circ}C$, and a $pm1.5 Hz $frequency drift over an oscillation frequency range from 712Hz to 6.3kHz. A total harmonic distortion of 0.3 percent has been measured for a 3.3kHz oscillation and the corresponding peak-to-peak amplitude was 1V. The experimental results for bandpass VCO are also presented.

• 전기전자학회논문지
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• 제12권3호
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• pp.172-175
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• 2008

An improved triangular/square-wave VCO using OTAs is presented. It consists of two OTAs, a timing capacitor, and a resistor. A prototype circuit built with commercially available components exhibits less than 0.01% nonlinearity in its current-to-frequency transfer characteristic from 0.2 to 14 kHz and 450 ppm/$^{\circ}C$ temperature coefficient of frequency over $-20^{\circ}C$ to $40^{\circ}$.

• 한국전기전자재료학회논문지
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• 제25권9호
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• pp.686-691
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• 2012

In this paper, we designed a Chua's chaotic circuit using transcondcutor based nonlinear resistor. Proposed chaotic circuit consist of L, C, R and transcondcutor based Chua's diode. We performed SPICE simulation for chaotic dynamics such as time seriesform, frequency analysis and phase plane of the circuit. Chaotic dynamics of the circuit was analysed according to MOS size variation of the operational transconductance amplifier. Also, we performed SPICE circuit analysis for temperature dependance of the circuit. SPICE results showed that chaotic dynamics of the circuit varied according to the temperature variation and chaotic signals were generated in specific temperature conditions.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.759-762
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• 2002

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOS-FET (FG-MOSFET) is proposed. The proposed-circuit is the grounded VCLVR consists of only an ordinary MOSFET and an FG-MOSFET. The advantage of the proposed VCLVR are low-voltage and wide-input range. Next, as applications, a floating-node voltage controlled variable resistor and an operational transconductance amplifier using the proposed VCLVRs are proposed. The performance of the proposed circuits are characterized through HSPICE simulations with a standard 0.6 ${\mu}$m CMOS process. simulations of the proposed VCLVR demonstrate a resistance value of 40 k$\Omega$ to 338 k$\Omega$ and a THD of less than 1.1 %.