• Convergence Security Journal
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• v.18 no.5_1
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• pp.67-73
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• 2018

From a software engineering point of view, tracing is a special form of logging that records program execution information. Tracers using dedicated hardware are often used because of the characteristics of tracers that need to generate and decode huge amounts of data in real time. Intel(R) PT uses proprietary hardware to record all information about software execution on each hardware thread. When the software execution is completed, the PT can process the trace data of the software and reconstruct the correct program flow. The hardware trace program can be integrated into the operating system, but in the case of the window system, the integration is not tight due to problems such as the kernel opening. Also, it is possible to trace only a single process and not provide a way to trace multiple process streams. In this paper, we propose a method to extend existing PT trace program to support multi - process stream traceability in Windows environment in order to overcome these disadvantages.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.483-488
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• 2004

For real-time applications, the underlying operating system (0S) should support timeliness guarantees of real-time tasks. However, most of current operating systems do not provide timely management facilities in an efficient way. There could be two approaches to support timely management facilities for real-time applications: (1) by modifying 0S kernel and (2) by Providing a middleware without modifying 0S. In our approach, we adopted the middleware approach based on the TMO (Time-triggerred Message-triggered Object) model which is a well-known real-tine object model. The middleware, named TMSOM (TMO Support Middleware) has been implemented on various OSes such as Linux and Windows XP/NT/98. In this paper, we mainly consider TMOSM implemented on Linux(TMOS/Linux). Although the real-time schedul-ing aIgorithm used in current TMOSM/Linux can produce an efficient real-time schedule, it can be improved for periodic real-time tasks by considering several factors. In this paper, we discuss those factors and propose an improved real-time scheduling algorithm for periodic real-time tasks, In order to simulate the performance of our algorithm, we measure timeliness guarantee rate for periodic real-time tasks. The result shows that the performance of our algorithm is superior to that of existing algorithm. Additionally, the proposed algorithm can improve system performance by making the structure of real-time middleware simpler.

• Journal of IKEEE
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• v.18 no.4
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• pp.471-477
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• 2014

In this paper, we propose a low-cost license plate recognition system based on smart cam system using Android. The proposed system consists of a portable device and server. Potable device Hardware consists of ARM Cortex-A9 (S5PV210) processor control unit, a power supply device, wired and wireless communication, input/output unit. We develope Linux kernel and dedicated device driver for WiFi module and camera. The license plate recognition algorithm is consisted of setting candidate plates areas with canny edge detector, extracting license plate number with Labeling, recognizing with template matching, etc. The number that is recognized by the device is transmitted to the remote server via the user mobile phone, and the server re-transfer the vehicle information in the database to the portable device. To verify the utility of the proposed system, user photographs the license plate of any vehicle in the natural environment. Confirming the recognition result, the recognition rate was 95%. The proposed system was suitable for low cost portable license plate recognition device, it enabled the stability of the system when used long time by using the Android operating system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1507-1514
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• 2016

Full-image guided filter reflects all pixels of image in filtering by using weight propagation and two-pass model, whereas the existing guide filter is processed based on the kernel window. Therefore the computational complexity can be improved while maintaining characteristics of guide filter, such as edge-preserving, smoothing, and so on. In this paper, we propose an efficient VLSI architecture for the full-image guided filter by analyzing the data dependency, the data frequency and the PSNR analysis of the image in order to achieve enough speed for various applications such as stereo vision, real-time systems, etc. In addition, the proposed efficient scheduling enables the realtime process by minimizing the idle period in weight computation. The proposed VLSI architecture shows 214MHz of maximum operating frequency (image size: 384*288, 965 fps) and 76K of gates (internal memory excluded).

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.35-41
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• 2014

In this paper, we proposed the implementation of software-based 2D BitBLT engine on the pSOS operating system and the operation of the BitBLT engine on patient monitoring device was verified. To verify the proposed method on the patient monitoring device, we designed prototype PCB board, and verified the operation. We designed the motherboard by using ARM9-based CPU. Because hardware-based BitBLT module was replaced with software-based one, CPU load problem was weighted. To solve this problem, w changed 400Mhz processor instead of 200Mhz processor. We implemented 2D BitBLT kernel module as a device driver which is one of the key elements of a graphics controller GUI in patient monitoring device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.50-57
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• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.7
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• pp.277-282
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• 2013

Recently, there is a growing need for an open software platform where developers easily write intelligent motion control applications for smart cars, smart robots, smart factories, and so on. To this end, a general-purpose operating system with rich functionalities and various hardware supports can be a candidate for such a platform, but it is known to have limitations in guaranteeing the responsiveness of individual applications. In this paper, to assess the suitability of Linux to be such a platform, we evaluate the real-time performance of Xenomai-patched Linux on an ARM-based processor Exynos4210 with motion control applications. Experimental results show that it is possible to stably provide motion cycle times below 1ms to such applications even with background workloads.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.6
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• pp.637-647
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• 2010

Recent embedded systems are being more complicated due to their hierarchical software architecture including operating systems. The performance of such complicated software architecture could not be well analyzed through separate analysis of each software layer; the combined effect and the interactions among the whole software layers should be considered. In this paper, we show the design and implementation of a performance analysis framework that enables hierarchical analysis of performance of Linux-based embedded systems considering interactions among the software layers. By using the proposed framework, we can obtain useful run-time information about a hierarchical software structure which usually consists of user-defined function layer, library function layer, system call layer, and kernel events layer. Experimental results reveal that the proposed framework could accurately identify the performance bottlenecks with the corresponding software layers during executions of target applications through the accompanying sub-steps of the analysis: the actual execution paths, the execution time of each observed event in each software layer, and the control flows across the software layers.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.2
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• pp.31-42
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• 2014

Debugger systems are necessary to apply dynamic program analysis when evaluating security properties of embedded system software. It may be possible to make the use of software-based debugger and/or DBI framework if target devices support general purpose operating systems, however, constraints on applicability as well as environmental transparency might be incurred thereby hindering overall analyzability. Analysis with JTAG (IEEE 1149.1) debugging devices can overcome these difficulties in that no change would be involved in terms of internal software environment. In that sense, JTAG API can facilitate to practically perform dynamic program analysis for evaluating security properties of target device software. In this paper, we introduce an implementation of JTAG API to enable analysis of ARM core based embedded systems. The API function set includes the categories of debugger and target device controls: debugging environment and operation. To verify API applicability, we also provide example analysis tool implementations: our JTAG API could be used to build kernel function fuzzing and live memory forensics modules.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.391-398
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• 2001

To design and develop secure operating systems, the BLP (Bell-La Padula) model that represents the MLP (Multi-Level Policy) has been widely adopted. However, user\`s security level in the most developed systems based on the BLP model is inherited to a process that is actual subject on behalf of the user, regardless whatever the process behavior is. So, there could be information disclosure threat or modification threat by malicious or unreliable processes even though the user is authorized in the system. These problems can be solved by defining the subject as (user, process) ordered pair and by defining the process reliability. Moreover, when the leveled programs which exist as objects in a disk are executed by a process and have different level from the process level, the security level decision problem occurs. This paper presents an extended BLP (E-BLP) model in which process reliability is considered and solves the security level decision problem. And this model is implemented into the Linux kernel 2.4.7.