• Steel and Composite Structures
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• v.38 no.3
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• pp.337-353
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• 2021

Micro-electro-mechanical systems (MEMS) are widely employed in sensors, biomedical devices, optic sectors, and micro-accelerometers. New reinforcement materials such as carbon nanotubes as well as graphene platelets provide stiffer structures with controllable mechanical specifications by changing the graphene platelet features. This paper deals with buckling analyses of functionally graded graphene platelets micro plates with two piezoelectric layers subjected to external applied voltage. Governing equations are based on Kirchhoff plate theory assumptions beside the modified couple stress theory to incorporate the micro scale influences. A uniform temperature change and external electric field are regarded along the micro plate thickness. Moreover, an external in-plane mechanical load is uniformly distributed along the micro plate edges. The Hamilton's principle is employed to extract the governing equations. The material properties of each composite layer reinforced with graphene platelets of the considered micro plate are evaluated by the Halpin-Tsai micromechanical model. The governing equations are solved by the Navier's approach for the case of simply-supported boundary condition. The effects of the external applied voltage, the material length scale parameter, the thickness of the piezoelectric layers, the side, the length and the weight fraction of the graphene platelets as well as the graphene platelets distribution pattern on the critical buckling temperature change and on the critical buckling in-plane load are investigated. The outcomes illustrate the reduction of the thermal buckling strength independent of the graphene platelets distribution pattern while meanwhile the mechanical buckling strength is promoted. Furthermore, a negative voltage, -50 Volt, strengthens the micro plate stability against the thermal buckling occurrence about 9% while a positive voltage, 50 Volt, decreases the critical buckling load about 9% independent of the graphene platelet distribution pattern.

• Current Photovoltaic Research
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• v.9 no.1
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• pp.6-10
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• 2021

The mesh mask screen, which is generally used for screen printing metallization of silicon solar cell, requires high squeegee pressure and low printing speed. These requirements are acting as a limiting factor in production yield in photovoltaic industries. In order to improve the productivity, a metal mask, which has high durability and high printing speed, has been researched. In this paper, the characteristics of each solar cell, in which electrodes were formed by using a metal mask and a mesh mask, were analyzed through recombination current density. In particular, the metal-induced recombination current density (Jom) representing the recombination of the emitter-metal interface was calculated using the shading method, and the resulting efficiency and open-circuit voltage were analyzed through the diode equation. As a result of analyzing the proportion of the metal-induced recombination current density to the total emitter recombination current density, it was analyzed that the reduction of the metal-induced recombination current density through the metal mask is an important factor in reducing the total recombination current density of the solar cell.

• Journal of the Korean Society of Marine Environment & Safety
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• v.27 no.1
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• pp.187-192
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• 2021

In this study, Inconel 625 was used as a thermal spray material to prevent dew point corrosion damage to the economizer tube, and sealing treatment was performed after applying the arc thermal spray coating technology. Various electrochemical experiments were conducted in the 0.5 wt% sulfuric acid solution to analyze the corrosion resistance of the thermal spray coating (TSC) layer. After the anodic polarization experiment, the degree of corrosion damage was determined through a scanning electron microscope and EDS component analysis. When measuring the open circuit potential, the effect of the sealing treatment was confirmed through stable potential formation of the TSC+sealing treatment (TSC+Sealing). As a result of the anodic polarization experiment, the passivation region was confirmed in TSC and TSC+Sealing, and corrosion resistance was improved as no corrosion damage was observed. In addition, the corrosion resistance of TSC+Sealing was the best when analyzing the corrosion potential and corrosion current density calculated by Tafel analysis.

• Korean Chemical Engineering Research
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• v.60 no.1
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• pp.7-11
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• 2022

In the membrane forming process of a proton exchange membrane fuel cell (PEMFC), drying and annealing heat treatment processes are required for performance and durability. In this study, the optimal annealing temperature for improving the durability of the polymer membrane was studied. It was annealed in the temperature range of 125~175 ℃, and thermal stability and hydrogen permeability were measured as basic data of durability at each annealing temperature. The electrochemical durability was analyzed by Fenton reaction and open circuit voltage (OCV) holding. The annealing temperature of 165 ℃ was the optimal temperature in terms of thermal stability and hydrogen permeability. In the Fenton reaction, the fluorine emission rate of the membrane annealed at 165 ℃ was the lowest, and the lifespan of the membrane annealed at 165 ℃ was the longest in the OCV holding experiment, confirming that 165 ℃ was the optimal temperature for the durability of the polymer membrane.

• Korean Journal of Materials Research
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• v.31 no.11
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• pp.619-625
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• 2021

Cu₂ZnSn(S,Se)₄ (CZTSSe) based thin-film solar cells have attracted growing attention because of their earth-abundant and non-toxic elements. However, because of their large open-circuit voltage (V_oc)-deficit, CZTSSe solar cells exhibit poor device performance compared to well-established Cu(In,Ga)(S,Se)₂ (CIGS) and CdTe based solar cells. One of the main causes of this large V_oc-deficit is poor absorber properties for example, high band tailing properties, defects, secondary phases, carrier recombination, etc. In particular, the fabrication of absorbers using physical methods results in poor surface morphology, such as pin-holes and voids. To overcome this problem and form large and homogeneous CZTSSe grains, CZTSSe based absorber layers are prepared by a sputtering technique with different RTA conditions. The temperature is varied from 510 ℃ to 540 ℃ during the rapid thermal annealing (RTA) process. Further, CZTSSe thin films are examined with X-ray diffraction, X-ray fluorescence, Raman spectroscopy, IPCE, Energy dispersive spectroscopy and Scanning electron microscopy techniques. The present work shows that Cu-based secondary phase formation can be suppressed in the CZTSSe absorber layer at an optimum RTA condition.

• Current Photovoltaic Research
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• v.9 no.4
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• pp.128-132
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• 2021

Advances in screen printing technology have been led to development of high efficiency silicon solar cells. As a post PERx structure, an n-type wafer-based rear side TOPCon structure has been actively researched for further open-circuit voltage (Voc) improvement. In the case of the metal contact of the TOPCon structure, the poly-Si thickness is very important because the passivation of the substrate will be degraded when the metal paste penetrates until substrate. However, the thin poly-Si layer has advantages in terms of current density due to reduction of parasitic absorption. Therefore, poly-Si thickness and firing temperature must be considered to optimize the metal contact of the TOPCon structure. In this paper, we varied poly-Si thickness and firing peak temperature to evaluate metal induced recombination (Jom) and contact resistivity. Jom was evaluated by using PL imaging technique which does not require both side metal contact. As a results, we realized that the SiN_x deposition conditions can affect the metal contact of the TOPCon structure.

• Current Photovoltaic Research
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• v.9 no.4
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• pp.145-159
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• 2021

Light soaking (LS) stability in polymer solar cells (PSCs) has always been a challenge to achieve due to unstable photoactive layer-electrode interface. Especially, the electron transport layer (ETL) and photoactive layer interface limits the LS stability of PSCs. Herein, we have modified the most commonly used and robust zinc oxide (ZnO) ETL-interface using an organic dye molecule and a co-adsorbent. Power conversion efficiencies have been slightly improved but when these PSCs were subjected to long term LS stability chamber, equipped with heat and humidity (45℃ and 85% relative humidity), an outstanding stability in the case of ZnO/dye+co-adsorbent ETL containing devices have been achieved. The enhanced LS stability occurred due to the suppressed interfacial defects and robust contact between the ZnO and photoactive layer. Current density as well as fill factors have been retained after LS with the modified ETL as compared to un-modified ETL, owing to their higher charge collection efficiencies which originated from higher electron mobilities. Moreover, the existence of less traps (as observed from light intensity-open circuit voltage measurements and dark currents at -2V) are also found to be one of the reasons for enhanced LS stability in the current study. We conclude that the mitigation ETL-surface traps using an organic dye with a co-adsorbent is an effective and robust approach to enhance the LS stability in PSCs.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.71-76
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• 2022

Since brightness is proportional to the operating current, a method of connecting several LEDs in series and driving with a constant current source is widely used for driving circuits of LED lights. Because several LEDs are connected in series, if some LEDs open due to a fault, the current path is broken and all other LEDs connected in series are turned off. In this paper, we designed a circuit to solve this problem by connecting a Zener diode having a breakdown voltage of about 0.4V higher than the LED operating voltage in parallel with each LED to create a current bypass in case of LED failure. Through simulations and experiments, it was confirmed that the current of the Zener diode hardly flows when the LED is operating normally, and that the Zener diode stably operates as a current bypass when the LED fails.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.