• New & Renewable Energy
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• v.2 no.3
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• pp.31-36
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• 2006

Superstrate pin amorphous silicon thin-film(a-Si:H) solar cells are prepared on $SnO_2:F$ and ZnO:Al transparent conducting oxides(TCO) in order to see the effect of TCO/p-layers on a-Si:H solar cell operation. The solar cells prepared on textured ZnO:Al have higher open circuit voltage VOC than cells prepared on $SnO_2:F$. Presence of thin microcrystalline p-type silicon layer(${\mu}c-Si:H$) between ZnO:Al and p a-SiC:H plays a major role by causing improvement in fill factor as well as $V_{OC}$ of a-Si:H solar cells prepared on ZnO:Al TCO. Without any treatment of pi interface, we could obtain high $V_{OC}$ of 994mV while keeping fill factor(72.7%) and short circuit current density $J_{SC}$ at the same level as for the cells on $SnO_2:F$ TCO. This high $V_{OC}$ value can be attributed to modification in the current transport in this region due to creation of a potential barrier.

• Journal of Information Display
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• v.10 no.4
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• pp.202-205
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• 2009

An automated circuit repair system was developed for enhancing the yield of nondefective liquid crystal panels, focusing on the resist patterns on the circuit material layer of thin-film transistor (TFT) substrates prior to etching. The developed system has an advantage over the parallel conventional system: In the former, the repair conditions depend on the type of resist whereas in the latter, the repair parameters must be fine-tuned for each circuit material. The developed system consists of a resist pattern defect inspection system and a pattern repair system for short and open defects. The repair system performs fine corrections of abnormal areas of the resist pattern. The open-repair system is equipped with a syringe to dispense resist. To maintain a stable resist diameter, a thermal insulator was installed in the syringe system. As a result, the diameter of the dispensed resist became much more stable than when no thermal insulator was used. The resist diameter was kept within the target of $400{\pm}100{\mu}m$. Furthermore, a prototype system was constructed, and using a dummy pattern, it was confirmed that the system worked automatically and correctly.

• Electrical & Electronic Materials
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• v.10 no.9
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• pp.930-937
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• 1997

Polycrystalline CdTe thin films have been studied for photovoltaic application because of their high absorption coefficient and optimal band energy(1.45 eV) for solar energy conversion. In this study CdTe thin films were deposited on CdS(chemical bath deposition)/ITO(indium tin oxide) substrate by rf-magnetron sputtering under various conditions. Structural optical and electrical properties are investigated with XRD UV-Visible spectrophotometer SEM and solar simulator respectively. The fabricated CdTe/CdS solar cell exhibited open circuit voltage( $V_{oc}$ ) of 610 mV short circuit current density( $J_{sc}$ ) of 17.2 mA/c $m^2$and conversion efficiency of about 5% at optimal sputtering conditions.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.341-342
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• 2007

The IRFPA (InfraRed Focal Plane Array) ROIC (ReadOut Integrated Circuit) was designed in folded-cascode Op-Amp using $0.35{\mu}m$ CMOS technology. As the folded-cascode has high open-loop voltage gain and fast settling time, that used in many analog circuit designs. In this paper, folded-cascode Op-Amp for ROIC of the $32{\times}32$ IRFPA has been designed. HSPICE simulation results are unit gain bandwidth of 13.0MHz, 90.6 dB open loop gain, 8 V/${\mu}m$ slew rate, 600 ns settling time and $66^{\circ}$ phase margin.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.300-300
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• 2010

후면 패시베이션, back contact의 가변, 후면 접촉면적의 가변 등으로 Laser Fired Contact 태양전지의 효율을 증가 시킬 수 있다. 이 중 spacing의 가변으로 후면 접촉 면적을 가변 할 수 있으며, 이로 인하여 LFC 태양 전지의 효율을 높일 수 있을 것으로 전망된다. 본 연구에서는 후면 접촉 면적을 가변하였으며 이에 따른 효과를 확인하였다. series resistance가 작고, open circuit voltage 가 높은 최적의 조건을 찾는 것에 그 목적을 두었다. 실험 순서는 texturing 후, 후면에 SiNx를 10nm 증착하였으며, drive-in 방법으로 $POCl_3$을 도핑하였다. ARC후, spacing 조건 가변으로 접촉 면적을 가변시키면서 소자의 특성 변화를 비교하였다. 접촉 면적 및 spacing 조건은 5개의 set에 대하여 reference, 50%의 접촉 면적을 가지는 $150{\mu}m$ line, 10%의 접촉 면적을 가지는 $700{\mu}m$ line, 1%의 접촉 면적을 가지는 $700{\mu}m$ dot, 그리고 0.2%의 접촉 면적을 가지는 $1500{\mu}m$ dot으로 하였다. 각각의 경우에 대한 short circuit current density, fill factor, seris resistance, sheet resistance, open circuit voltage를 측정하였으며, 특히 series resistance는 각각의 경우에 대하여 $6.1m{\Omega}$, $5.1m{\Omega}$, $7.8m{\Omega}$, $10.1m{\Omega}$, 그리고 $15.7m{\Omega}$으로 측정되었다. wafer의 외각 테두리를 접촉 면적이 증가함에 따라서 sheet resistance가 증가하는 것을 확인 할 수 있었다.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.158-161
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• 2006

Superstrate pin amorphous silicon thin-film (a-Si:H) solar cells are prepared on $SnO_2:F$ and ZnO:Al transparent conducting oxides (TCO) In order to see the effect of TCO/P-layers on a-Si:H solar cell operation. The solar cells prepared on textured ZnO:Al have higher open circuit voltage $V_{oc}$ than cells prepared on $SnO_2:F$. Presence of thin microcrystalline p-type silicon layer $({\mu}c-Si:H)$ between ZnO:Al and p a-SiC:H plays a major role by causing improvement in fill factor as well as $V_{oc}$, of a-Si:H solar cells prepared on ZnO:Al TCO. Without any treatment of pi interface, we could obtain high $V_{oc}$, of 994mv while keeping fill factor (72.7%) and short circuit current density $J_{sc}$ at the same level as for the cells on $SnO_2:F$ TCO. This high $V_{oc}$ value can be attributed to modification in the current transport in this region due to creation of a potential barrier.

• Journal of the Korean Society of Safety
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• v.28 no.2
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• pp.26-30
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• 2013

The purpose of this study is to find risk factors by analyzing the operation principle of a photo coupler (P/C) used to remove the noise of electronic devices and establish a base for the performance improvement of developed products. It was found from the P/C circuit analysis of normal products that they were equipped with an electrolytic condenser of $0.1{\mu}F$ to smooth system signals. Due to the epoxy resin packing the external part of the P/C, this study experienced a limit to visually examine the damage to it. It could be seen from the analysis of electric characteristics of the P/C that the forward voltage ($V_f$) and reverse current ($I_r$) were 1.3 V and 10 uA, respectively. In addition, it is required that the breakdown voltage (VCE) between the collector (C) and emitter (E) be maintained at less than 35 V. The and of the damaged product #1 were comparatively good. However, the measurement of was 100.0 uA. From this, it is thought that a short circuit occurred to the internal circuit. Moreover, from the fact that the of the damaged product #2 was open circuit and the measurement of was 0.0 uA, it is thought that the collector and emitter was separated or insulation resistance was significantly high. Furthermore, from the fact that the of the damaged product #3 was open circuit and the measurement of was 0.0 uA, it is thought that the space between the collector (C) and emitter (E) failed to meet the design standard or that they were separated. Therefore, it is thought that fabricating the P/C by increasing the reverse current 10 mA to 50 mA will prevent its malfunction.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.39-42
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• 2018

In this paper, a low-power MPPT interface circuit for vibration energy harvesting sources is presented. The designed circuit rectifies the harvested ac type energy to the dc type energy required to drive the system, and periodically samples and holds the open circuit voltage (Voc) through the MPPT controller, and transfers the harvested power to the load while maintaining the input voltage at 1/2 of the maximum available power point. All circuits have been designed using a 0.35-um CMOS technology, and the operation has been verified through simulation. Simulation results show that the designed circuit consumes 98nA of current at 3V input voltage and the maximum power efficiency is 99.21%. The designed chip occupies $1.281mm{\times}1.236mm$.

• Journal of Mechanical Science and Technology
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• v.17 no.6
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• pp.816-824
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• 2003

In this study, variations of cutting performance with pulse time, open circuit voltage, wire speed and dielectric fluid pressure were experimentally investigated in Wire Electrical Discharge Machining (WEDM) process. Brass wire with 0.25 mm diameter and AISI 4140 steel with 10 mm thickness were used as tool and work materials in the experiments. The cutting performance outputs considered in this study were surface roughness and cutting speed. It is found experimentally that increasing pulse time, open circuit voltage, wire speed and dielectric fluid pressure increase the surface roughness and cutting speed. The variation of cutting speed and surface roughness with cutting parameters is modeled by using a regression analysis method. Then, for WEDM with multi-cutting performance outputs, an optimization work is performed using this mathematical models. In addition, the importance of the cutting parameters on the cutting performance outputs is determined by using the variance analysis (ANOVA).

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.143-148
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• 2004

This paper presents the two modes for maximum power point tracking of the photovoltaic system. The method combines the merits of the two methods consisting of the open circuit method and the three point weight comparison method. The maximum point found by this method is exactly than by the open circuit method. By the simulation results, the actual maximum point can be found that is better than the Perturb and Observe (P&O) method or the three point weight method only one method, especially, in the case of non regular pattern of Power-Voltage (P-V) curve.