• Journal of Korean Institute of Industrial Engineers
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• v.24 no.1
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• pp.95-103
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• 1998

This paper deals with technology relevance analysis, which measures technological dependency between needs technology and its component technology as well as between needs technologies. The two-round survey was carried out: In the first round, a wide range of needs technologies in construction and building industry were identified and classified to meet a variety of social needs which were anticipated in the near future of Korea. In the second, relevance between needs technology and its component technologies was checked by some 120 experts. Based on the survey results, the individual relevances among needs technologies were computed. Finally the ranking of needs technologies in construction industry was set according to the degree of technology relevance. This relevance is to be used as one of criteria for the selection of national R&D projects which the Ministry of Construction and Transportation plans to promote in the next five years.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 1999.03b
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• pp.95-98
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• 1999

In this study, a method to find the optimal intermediate die geometry for the multi-stage drawing process for the rectangular rod from a round bar is proposed and a program using the proposed method is developed. On the stage of the design of the intermediate die geometry, the virtual die was constructed using the initial billet as a inlet of the drawing die and the final product as a exit of that and the virtual die was divided by the number of pass. Divided die was transformed into the rectangular one which is the intermediate die geometry for the multi-stage rectangular drawing process. In order to verify the application of the proposed method on the real industrial product, the drawing of the rectangular rod from a round which composed two stage has been performed and simulated by the three dimensional rigid plastic finite element method.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.10 no.3
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• pp.348-357
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• 1998

The flow characteristics inside U-bend tube of the laminated plate heat exchanger were numerically investigated. The behavior of fluid flow, and the variations of the faulty area and friction factor are examined according to the distance between the span and the wall and the diameter of the round attacked to the end of span. The results show that the diameter(d) of the round attached to the span is mainly associated with the smooth circulation of fluid flow rather than the size of faulty area and the friction factor. As the distance($\ell$) between the span and the wall decreases, the faulty area decreases, however the friction factor dramatically increases. It is also found that one can obtain a good result in the view of the flow characteristics and pressure drop at d=7.5mm and $\ell$=30.5mm.

• Proceedings of the Korean Society of Sericultural Science Conference
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• 2003.04a
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• pp.65-65
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• 2003

Artificial hibernation is essential for year-round rearing of the bumblebee, Bombus ignitus that undergoes one generation per year It is known that keeping the queens in low temperature for two or three months is effective to terminate their diapause and develop the colony. Temperature, time and surroundings to keep the queens during artificial hibernation were investigated. (omitted)

• Tuberculosis and Respiratory Diseases
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• v.38 no.2
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• pp.207-211
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• 1991

A 31-year-old male has a $11.5{\times}10\;cm$ sized relatively well marginated round mass containing peripheral calcification in left upper lung field on chest roentgenograms and computed tomogram. There are no presenting symptoms including weight loss, and occupational exposures. Definitive diagnosis must differentiate from the variety of diseases whether malignancy or benign, extrapulmonary or intrapulmonary. This report described one case of malignant localized fibrous mesothelioma histologically.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1478-1482
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• 2003

In this paper. Rijndael cipher algorithm is implemented by a hardware. It was selected as the AES(Advanced Encryption Standard) by NIST. It has structure that round operation divided into 2 subrounds and subrounds are pipelined to calculate efficiently. It takes 5 clocks for one-round. The AES-128 cipher algorithm is implemented for hardware by ALTERA FPGA, and, analyzed the performance. The AES-128 cipher algorithm has approximately 424 Mbps encryption rate for 166Mhz max clock frequency. In case of decryption, it has 363 Mbps decryption rate fu 142Mhz max clock frequency. In case of cipher core, it has 320Mbps encryptionㆍdecryption rate for 125Mhz max clock frequency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.796-800
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• 2011

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.11a
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• pp.475-478
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• 2005

Calculation of wear depth with regard to the wear topology is peformed numerically Four typical wear topology, that is round, crescent, flat, and diamond types are adopted to represent the configuration of wear volume. Diamond and flat types are the most severe topology for wear depth history, whereas round and crescent types have small increasing rate of wear depth to the wear volume. Based on this study we can guess that the most severe wear phenomena happens to be upper side of U-tubes in the KSNP SG, because flat or diamond wear will be generated by the wearing motion between tubes and diagonal, vertical, horizontal strips. The misalignment of tube at the stage of manufacturing or distortion of upper structure due to the thermal expansion or vibration of upper structure such as diagonal, vertical, and horizontal strips will be one of the main causes of flat or diamond wear.

• International Journal of Computer Science & Network Security
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• v.21 no.12spc
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• pp.451-458
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• 2021

Providing a secure and effective way to protect confidential and private data is an urgent process, and accordingly, we will present in this research paper a new method, which is called multiple rounds variable block method (MRVB) which depends on the use of a colored image that is kept secret to generate needed work and round keys. This method can be used to encrypt-decrypt data using various lengths private key and data blocks with various sizes. The number of rounds also will be variable starting from one round. MRVB will be implemented and compared with the encryption-decryption standards DES and AES to show the improvements provided by the proposed method in increasing the security level and in increasing the throughput of the process of data cryptography. The generated private key contents will depend on the used image_key and on the selected number of rounds and the selected number of bytes in each block of data.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.4
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• pp.372-381
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• 2001

In this paper SEED, the Korea Standard 128-bit block cipher algorithm is implemented with VHDL and mapped into one FPGA. SEED consists of round key generation block, F function block, G function block, round processing block, control block and I/O block. The designed SEED is realized in an FPGA but we design it technology-independently so that ASIC or core-based implementation is possible. SEED requires many hardware resources which may be impossible to realize in one FPGA. So it is necessary to minimize hardware resources. In this paper only one G function is implemented and is used for both the F function block and the round key block. That is, by using one G function sequentially, we can realize all the SEED components in one FPGA. The used cell rate after synthesis is 80% in Altem FLEXI0KlOO. The resulted design has 28Mhz clock speed and 14.9Mbps performance. The SEED hardware is technology-independent and no other external component is needed. Thus, it can be applied to other SEED implementations and cipher systems which use SEED.