• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.463-467
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• 2000

In this paper, we have implemented the Web Server Patient Monitoring System using PPP. It is composed of two parts. The first part is the Analog board for acquiring ECG signals. The second part is the module for processing and transmitting the acquired signal. The second part is using PPP for dial-up networking, TCP/IP for Internet, HTTP for web browser and JAVA program for a Patient Monitoring Program in one chip. In home, it is not need to establish another network line because it uses a telephone line. And a user who want to monitor a patient's biosignal can monitor a patient without wholly open network because it is the network sewer. The Patient Monitoring Program runs on a web browser by downloaded JAVA codes when a user connect to this system. It can make the Home Patient Monitoring Program decrease cost. It can help to avoid the limitation of monitoring a patient.

• Animal Bioscience
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• v.36 no.1
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• pp.10-18
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• 2023

Objective: In this study, we aimed to position the Hungarian Merino among other Merinoderived sheep breeds, explore the characteristics of our sampled animals' genetic similarity network within the breed, and highlight single nucleotide polymorphisms (SNPs) associated with daily weight-gain. Methods: Hungarian Merino (n = 138) was genotyped on Ovine SNP50 Bead Chip (Illumina, San Diego, CA, USA) and positioned among 30 Merino and Merino-derived breeds (n = 555). Population characteristics were obtained via PLINK, SVS, Admixture, and Treemix software, within-breed network was analysed with python networkx 2.3 library. Daily weight gain of Hungarian Merino was standardised to 60 days and was collected from the database of the Association of Hungarian Sheep and Goat Breeders. For the identification of loci associated with daily weight gain, a multi-locus mixed-model was used. Results: Supporting the breed's written history, the closest breeds to Hungarian Merino were Estremadura and Rambouillet (pairwise F_ST values are 0.035 and 0.036, respectively). Among Hungarian Merino, a highly centralised connectedness has been revealed by network analysis of pairwise values of identity-by-state, where the animal in the central node had a betweenness centrality value equal to 0.936. Probing of daily weight gain against the SNP data of Hungarian Merinos revealed five associated loci. Two of them, OAR8_17854216.1 and s42441.1 on chromosome 8 and 9 (-log₁₀P>22, false discovery rate<5.5e-20) and one locus on chromosome 20, s28948.1 (-log₁₀P = 13.46, false discovery rate = 4.1e-11), were close to the markers reported in other breeds concerning daily weight gain, six-month weight, and post-weaning gain. Conclusion: The position of Hungarian Merino among other Merino breeds has been determined. We have described the similarity network of the individuals to be applied in breeding practices and highlighted several markers useful for elevating the daily weight gain of Hungarian Merino.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.12 s.103
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• pp.1206-1212
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• 2005

In this paper, we propose a novel antenna structure which uses the electric and magnetic currents so as to eliminate nulls on their radiation pattern. The tag antenna was matched to the conjugate impedance of the commercial tag chip using the modified double T matching network. The radiation efficiency is about $90\%$, and the bandwidth($S_{11}< -10 dB$) is 848${\~}$926 MHz. Also it shows the gain deviation between the maximum and minimum gains about 4 dB at any direction of the tag antenna at the operating frequency. The readable range of the tag is 1.7${\~}$2.4 m for an arbitrary rotation angle of the tag with a commercial tag chip.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.1
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• pp.53-64
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• 2009

For a realization of the ubiquitous society, applying IT to vehicle industry has recently been an attractive issue to make wireless communication in body area network possible to everywhere. In this paper, we propose the physical layer symbol structure based on PPM scheme of the IEEE 802.15.4a for the off-body high data rate WBAN system. We propose four symbol structures which is classified according to the number of the chip and whether the channel coding is used or not. We calculate the required SNR through the link budget calculation and the recently proposed off-body WBAN channel environment was applied in the simulation. The results of four systems show that small number of burst's chip enhances the performance and the system is capable to achieve the data rate of 10 Mbps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.3 s.118
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• pp.298-304
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• 2007

In this paper, the antenna which has a multiband operation (GSM850, EGSM, DCS1800, USPCS, W-CDMA) is proposed. This antenna was designed by the commercial software HFSS 3-D EM simulator, and it is organized by using a meander branch structure which has a via and lines on FR-4$(\varepsilon_r=4.4)$ substrate. Especially, it has a gap feeding structure which makes good operation at overall bandwidth. The designed antenna is manufactured by PCB processing, and measured by using a network analyzer and a test chamber. The manufactured antenna with the dimension of 8 mm width, 20 mm height and 3.2 mm thickness is able to applied as an internal antenna for multiband mobile phones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.15-22
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• 2004

This paper presents the channel analysis considering power distribution network(PDN) system of PCB. For achieve the target PDN system we proposed the useful design approach for acquiring the characteristic target of power distribution network in overall frequency ranges. The proposed method is based on the hierarchical approach related to frequency ranges and the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors and the board through it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. The analysis of PDN system shows that although the effective inductance of package dominatly affects the power noise and the signal transfer through data channel, the board PDNs also can not be neglected for achieving the accurate channel signaling. Therefore, we must design concurrently the chip, package, and board from the initial spec design of high speed digital system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.339-345
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• 2016

This paper presents a two-stage power amplifier MMIC using a $0.4{\mu}m$ GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of $2.0{\times}1.9mm^2$ and was mounted on a $4{\times}4$ QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.8
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• pp.610-618
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• 2017

This paper presents a 868/915 MHz CMOS RF transceiver for the ZigBee application. Using a switchless matching network, the off chip switch is removed to achieve the low cost RF transceiver, and by the elimination of the switch's insertion loss we can achieve the benefits for the RF receiver's noise figure and transmitter's power efficiency at the given output power. The receiver is composed of low-noise amplifier, mixer, and baseband analog(BBA) circuit. The transmitter is composed of BBA, mixer, and driver amplifier. And, the integer N type frequency synthesizer is designed. The proposed ZigBee RF full transceiver is implemented on the $0.18{\mu}m$ CMOS technology. Measurement results show that the maximum gain and the noise figure of the receiver are 97.6 dB and 6.8 dB, respectively. The receiver consumes 32 mA in the receiver mode and the transmitter 33 mA in the transmission mode.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.165-171
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• 2019

The study of the computer architecture has shown that major improvements in price-to-energy performance stems from domain-specific hardware development. This paper analyzes the tensor processing unit (TPU) ASIC which can accelerate the reasoning of the artificial neural network (NN). The core device of the TPU is a MAC matrix multiplier capable of high-speed operation and software-managed on-chip memory. The execution model of the TPU can meet the reaction time requirements of the artificial neural network better than the existing CPU and the GPU execution models, with the small area and the low power consumption even though it has many MAC and large memory. Utilizing the TPU for the tensor flow benchmark framework, it can achieve higher performance and better power efficiency than the CPU or CPU. In this paper, we analyze TPU, simulate the Python modeled OpenTPU, and synthesize the matrix multiplication unit, which is the key hardware.