• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.221-222
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• 2011

본 논문은 인버터의 PWM구동 시 출력 전류에 발생하는 DC offset을 제거 하는 방법을 제안한다. 인버터의 PWM구동 시 소자 단락을 막기 위해 필수적으로 적용하는 deadtime과 각 스위치 소자의 voltage drop으로 인해 출력에 왜곡이 발생한다. 이상적인 스위치인 경우에는 이 두 가지의 왜곡을 feedforward로 보상하면 된다. 하지만 스위치 소자가 이상적이지 않기 때문에 각 스위치 소자의 voltage drop의 차이와 on & off time delay의 차이는 출력 전류에 DC offset을 발생시킨다. 따라서 deadtime과 스위치 voltage drop에 대한 보상과 함께 출력 전류의 DC offset을 feedback으로 하여 보상되지 못한 왜곡을 추가적으로 보상하여 결론적으로 출력 전류의 DC offset을 제거할 수 있게 하였다. 제안된 기법은 시뮬레이션을 통하여 그 타당성을 확인하였다.

• Journal of the Korean Solar Energy Society
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• v.37 no.6
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• pp.1-12
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• 2017

The DC link of Grid-Connected 3-Phase 3-Level T-type Photovoltaic PCS (PV-PCS) consists of two series connected capacitors for using their neutral voltage. The mismatch between two capacitor characteristics and transient states happened in load change cause the imbalance of neutral voltage. As a result, PV-PCS performance is degraded and the system becomes unstable. In this paper, a mathematical model for analyzing the imbalance of neutral voltage is derived and a compensation method using offset voltage is proposed, where offset voltage adjusts the applying time of P-type and N-type small vectors. The validity of the proposed methods is verified by simulation and experiment.

• Journal of Sensor Science and Technology
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• v.7 no.5
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• pp.300-305
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• 1998

In this paper, integrated pressure sensor with calibration of offset voltage and full scale output and temperature compensation of offset voltage and full scale output were designed. The signal conditioning circuitry are designed that calibrate the offset voltage and full scale output to desired values and minimize the temperature drift of offset voltage and full scale output. Designed circuits are simulated using SPICE in a bipolar technology. The ion implanted resistor of different temperature coefficient were used to trimming the desired values. As a results, offset voltage was calibrated to 0.133V and the temperature drift of offset voltage was reduced to $42\;ppm/^{\circ}C$. Also, the full scale output was calibrated to 4.65V and the temperature coefficient of full scale output was reduced to $40ppm/^{\circ}C$ after temperature compensation.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.86.3-86
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• 2001

Hall effect sensor using 7um, 1.7 ohm-cm or 10um, 3.5 ohm-cm Bipolar process was successfully developed. The Hall sensor consists of various patterns, such as regular shapes, rectangles, diamond, hexagon and cross shapes to optimize offset voltage and sensitivity for proper applications. In order to measure offset voltage in chip scale the Agilent company´s 4156C and Nano-Voltage Meter were used and the best structure in offset voltage was finally selected by using ceramic package. The patterns appear to be the quadri-rectangular patterns entirely and three-parallelogram patterns. The measured offset voltages were found to be about 173-365uV. Meanwhile, in ...

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.67-75
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• 2007

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.828-835
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• 2001

Novel bipolar transresistance amplifier(TRA) and its offset-compensated TRA for high-performance current-mode signal processing are described. The TRA consist of two current follower for a current inputs, a current summer for the current-difference, a resistor for the current to voltage converter, and a voltage follower for the voltage output. The offset-compensated TRA adopts diode-connected npn and pnp transistor to reduce offset voltage in the TRA. The simulation results show that the TRA has impedance of 0.5 Ω at the input and the output terminal. The offset voltages at these terminals is 40 mV The offset-compensated TRA has the offset voltage of 1.1 mV and the impedance of 0.25 Ω. The 3-dB cutoff frequency is 40 MHz for the two TRA＇s when used as a current to voltage converter with unit-gain transresistance. The power dissipation is 11.25 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.44-54
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• 2001

In this paper, a novel test method is proposed to detect the hard and soft fault in analog circuits. The proposed test method makes use of the offset voltage, which is one of the op-amps characteristics. During the test mode, CUT is modified to unit gain op-amps with feedback loop. When the input of the op-amp is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage. Faults in the op-amp which cause the offset voltage exceeding predefined range of tolerance can be detected. In the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time and cost is reduced. In this note, the validity of the proposed test method has been verified through the example of the dual slope A/D converter. The HSPICE simulations results affirm that the presented method assures a high fault coverage.

• Analytical Science and Technology
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• v.14 no.6
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• pp.486-493
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• 2001

The effect of SIMS analysis conditions such as mesh grid, offset voltage and ion species on the in-depth profile for bismuth titanate thin film was examined in terms of charging effect and detection limit. The results shows that the use of offset voltage -40 V reduces the charging effect and the detection limit. The employment of mesh grid in sample preparation leads to the reduction of the charging effect in small amount, but deteriorate the detection limit. Utilization of primary $O^-$ ion for SIMS analysis of bismuth titanate thin film showed almost the same effect as using offset voltage -40 V. However, it takes approximately triple acquisition time than using $O_2{^+}$ ion due to the poor beam current of the source in the experiment.

• Journal of the Korean Solar Energy Society
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• v.32 no.spc3
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• pp.255-261
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• 2012

Since PV PCS uses output current sensor for ac output current control, the sensor's sensing value includes unnecessary offset inevitably. If PV inverter is controlled by the included offset value, it's output current will generate DC offset. The DC offset of output current for trans-less PV inverter is fatal to grid, which results in saturating grid side transformer. Usually DSP controller of PV inverter reads several times sensing value during initial operation and, finally, it's average value is used for offset calibration. However, if temperature changes, the offset changes, too. And also, the switch device is not ideal, both each switching element of the voltage drop difference and on & off time delay difference generate DC offset. Thus, to compensate for deadtime and the switch voltage drop, feedback control by output current DC offset should be provided to compensate additional distortion of the output current. The validity of the proposed method is confirmed through PSIM simulation.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1496-1504
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• 2019

This paper proposes a new THD reduction algorithm for modular multilevel converters (MMCs) with offset voltage injection operated in nearest level modulation (NLM). High voltage direct current (HVDC) is actively introduced to the grid connection of offshore wind powers, and this paper deals with a voltage generation technique with an MMC for wind power generation. In the proposed method, third harmonic voltage is added for reducing the THD. The third harmonic voltage is adjusted so that each of the pole voltage magnitudes maintains a constant value with a maximum number of (N+1) levels, where N is the number of sub-modules per arm. By using the proposed method, the THD of the output voltage is mitigated without increasing the switching frequency. In addition, the proposed method has advantageous characteristics such as simple implementation. As a part of this study, this paper compares the THD results of the conventional method and the proposed method with offset voltage injection to reduce the THD. In this paper, simulations have been carried out to verify the effectiveness of the proposed scheme, and the proposed method is implemented by a HILS (Hardware in the Loop Simulation) system. The obtained results show agreement with the simulation results. It is confirmed that the new scheme achieved the maximum level output voltage and improved the THD quality.