• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.7
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• pp.635-645
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• 2016

In this paper, we showed the phase noise of voltage controlled oscillator(VCO) can be radically improved using FLL(Frequency Locked Loop). At first, a 5 GHz VCO is fabricated using a hair-pin resonator. The fabricated VCO shows a phase noise of -53.1 dBc/Hz at 1 kHz frequency offset. In order to improve the phase noise of the fabricated VCO, a FLL is constructed using the feedback loop that consists of the VCO, a frequency detector composed of 5 GHz resonator, loop-filter, and level shifter. The fabricated FLL is designed to oscillate at a frequency of 5 GHz, and its measured phase noise is about -120.6 dBc/Hz at 1 kHz offset frequency. As a result, the phase noise of VCO can be radically improved by about 67.5 dB applying FLL. In addition, the measured phase noise performance is close to that of crystal oscillator.

• The Journal of the Acoustical Society of Korea
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• v.16 no.4
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• pp.76-84
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• 1997

In this paper, one of the core components of a mobile communication system, VCO(Voltage Controlled Oscillator) IC is designed. The VCO IC was designed, have realized as LC turned oscillator using varicap. LC sinusoidal tuned oscillator generally requires external inductors and thus remainding circuit is implemneted in monolithic IC. The circuit is fabricated using an 15 mask IC process and has a die size of 1150um${\times}$780um. The tests showed that VCO was operated at frequencies in the regions between 880MHz-915MHz in the control voltage range of 1V to 3V at 5V supply voltage and as the power supply was varied from 4.5V to 5.5V, the frequency varied 425KHz/V. The VCO IC has frequency shift of 1.97MHz/T, carrier level of -7dBm and power consumption of 16.7mA. Also it has phase noise of -80dBc/Hz, offset at 50KHz and harmonic response of center frequency is -41dBm. For the future development of the transceiver 1 chip, the previously mentioned external devices need to be incorporated into Si MMIC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.3
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• pp.185-191
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• 2018

In this paper, an improved Norton amplifier is proposed and the problems caused by the current input in the Norton amplifier, which has advantages in current transmission, are analyzed. The output of the voltage follower consisting of an operational-amplifier with constant output voltage characteristics is used as an input terminal of the proposed circuit. It is configured to detect the power supply current passing through the voltage follower and extract the current from the input terminal. The performance of the improved Norton amplifier is verified at experiment according to the input current. The results are compared with conventional Norton amplifier. Consequently, the input offset voltage, which is a problem in the conventional Norton amplifier, was removed in the proposed circuit. In addition, the average error of the output voltage with respect to the input current was reduced to 4.755%. It is verified that the characteristics of the proposed circuit are improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2260-2266
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• 2009

In this paper, the problem of electromagnetic coupling between a slit fed by a flanged parallel-plate waveguide (FPPW) and a nearby conducting strip parallel to the slit is studied as a simplified problem for a near-field scanning microscopy (NSM). The characteristics of the FPPW are investigated from the results for the variations of the equivalent slit admittance, the reactive powers near the slit inside and outside the FPPW, the magnitude and phase of the voltage reflection coefficient of the TEM wave. The performance of the proposed apparatus as an NSM is tested by examining the effects of various geometrical parameters such as guide height, slit width, strip width, distance between slit and strip, and the ratio of slit width to guide height on the magnitude and phase of the voltage reflection coefficient of the TEM wave. From the results for the voltage reflection coefficient against the strip offset from the slit, it is found that a slit in the FPPW with smaller guide height gives higher scanning resolution and the phase variation is more sensitive than the magnitude variation.

• Journal of IKEEE
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• v.18 no.1
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• pp.119-127
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• 2014

This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor ${\Sigma}{\Delta}$ modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and ${\Sigma}{\Delta}$ modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.4 no.2 s.7
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• pp.81-87
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• 2005

In this paper, a VCDRO(Voltage Control Dielectirc Resonator Oscillator) for signal source of doppler radar system is designed and fabricated. The proposed VCDRO is made with new tuning mechanism using CPW line. The coplanar waveguide of $\lambda_{g}$/2 in length with varactor diode is placed on the metallization side under the dielectric resonator and coupled to it. Tuning varactor diode is mounted at one end of the CPW. The proposed circuit tuned by a CPW allows one more varactor diode to be mounted on the optimized CPW, where a greater sensitivity of frequency tuning is needed. With varying the biasing voltage for the varactor diode from 0 V to 15 V, output frequency tuning of 12 MHz is obtained. The PLDRO exhibits output power of 16.5 dBm with phase noise in the phase locked state characteristic of -115 dBc/Hz at 100 Hz, -105 dBc/Hz at the 10 kHz, and -102 dBc/Hz at 1 Hz offset from 10.525 GHz , respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.401-408
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• 2001

This paper shows the design, fabrication and performance analysis of VCO which plays a major role in 5.8 GHz RF module for ITS. The design specifications of the VCO are determined on the basis of 5.8 GHz RF modul performance requirements. The design parameters are optimized through ADS simulation tool. The operating characteristic and performance analysis of the implemented VCO based on the design parameters are accomplished. The frequency variations according to the voltage change(0 ~5 V) of varactor diode are from 5.42 GHz to 5.518 GHz and the power level is 6.5 dBm. The second harmonic suppression are -21.5 dBc at 5.51 GHz and the phase noise characteristics are -83.81 dBc at 10 kHz offset frequency. The implemented VCO is available to not only DSRC and also, 5.8 GHz other systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.212-215
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• 2016

In this paper, a 5.08 GHz Ring Voltage Controlled Oscillator(Ring VCO) was implemented using $0.18{\mu}m$ standard CMOS technology. The proposal Ring VCO is 3-stage structure. This research confirmed that the each stage's different transistor size ratio influence the current change and alter power consumption consequentially. This circuit is formed to control the current thereby adding the Current Mirror and to tune the frequency by supplying control voltage. It has an 65.5 %(1.88~5.45 GHz) tuning range. The measured output power is -0.30 dBm. The phase noise is -87.50 dBc/Hz @1 MHz offset with operating frequency of 5.08 GHz fundamental frequency. The total power consumption of Ring VCO is 31.2 mW with 2.4 V supply voltage.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.242-249
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• 2011

The proposed converter has easy device selection for high step-up and high power applications since boost half bridge and voltage doubler cells are connected, respectively, in parallel and series in order to increase output power and voltage. Especially, optimized design of high frequency transformers is possible owing to reduced turn ratio and eliminated dc offset, and distributed power through three cores is beneficial to low profile and thermal distribution. The proposed converter does not necessitate start-up circuit and additional clamp circuit due to the use of whole duty range between 0 and 1 and is suitable for applications with wide input voltage range. Also, high efficiency can be achieved since ZVS turn on of switches are achieved in wide duty cycle range and ZCS turn on and off of diodes are achieved. The proposed converter was validated through 5 kW prototype.