• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1265-1267
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• 1993

The switching and the retention characteristics with the injection conditions(pulse height and pulse width) were investigated in the nonvolatile MNOS memories with thin oxide layer of $23{\AA}$ thick. The shift of flatband voltage was measured using the fast ramp C-V method and experimental results were analized using the previously developed models. It was shown that the experimental results were described quit well by the trap-assisted and modified Fowler-Nordheim tunneling models for the voltage pulse of $15V{\sim}19V,\;24V{\sim}25V$, respectively. However, the direct tunneling model was agreement with experimental values in all range of pulse height. As increasing the initial shift of the flatband voltage, the decay rate was increased. But for the same initial shift of the flatband voltage, the decay rate was smaller for low and long pulse than for high and short one.

• 한국결정성장학회지
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• 제14권4호
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• pp.151-154
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• 2004

Issues of ferroelectric high-density memories (>64 Mb) indispensable for upcoming ubiquitous era have been on the cell integration less than $0.1\;\mu\textrm{m}^2$ and reliabilities. Thus nanoscale control of microstructures of ferroelectric films with large switching polarization has been one of the issues to obtain the uniform electrical properties for realization of high-density memories. In this study the grain orientations and distributions of BT-based films by spin-on coatings were examined by FEG-SEM/EBSD. Ferroelectric domain characteristics by PFM were also performed to study the dependence of reliabilities on the grain orientations and distributions. It is believed that understandings of the nucleation and growth mechanisms of the a- or b-axis oriented films during the thermal processes such as RTA and furnace annealing affecting on grain orientation and uniformity could be possible based on our experimental results.

• 한국세라믹학회지
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• 제41권4호
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• pp.273-276
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• 2004

Report ferroelectric memories based on 0.35$\mu\textrm{m}$ CMOS technology ensuring ten-year retention and imprint at 175$^{\circ}C$. This excellent reliability resulted from newly developed BT-based ferroelectric films with superior reliability performance at high temperatures, and also resulted from robust integration schemes free from ferroelectric degradation due to process impurities such as moisture and hydrogen. The superior reliabilities at high temperature of ferroelectric memories using BT-based films are due to the random orientation by special bake treatments.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.28.2-28.2
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• 2011

Resistance random access memory (ReRAM) is a promising candidate for next-generation nonvolatile memory because of its advantageous qualities such as simple structure, superior scalability, fast switching speed, low-power operation, and nondestructive readout. We investigated the resistive switching behavior of tantalum oxide that has been widely used in dynamic random access memories (DRAM) in the present semiconductor industry. As a result, it possesses full compatibility with the entrenched complementary metal-oxide-semiconductor processes. According to previous studies, TiN is a good oxygen reservoir. The TiN top electrode possesses the specific properties to control and modulate oxygen ion reproductively, which results in excellent resistive switching characteristics. This study presents fully room temperature fabricated the TiN/$TaO_x$/Pt devices and their electrical properties for nonvolatile memory application. In addition, we investigated the TiN electrode dependence of the electrical properties in $TaO_x$ memory devices. The devices exhibited a low operation voltage of 0.6 V as well as good endurance up to $10^5$ cycles. Moreover, the benefits of high devise yield multilevel storage possibility make them promising in the next generation nonvolatile memory applications.

• 사물인터넷융복합논문지
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• 제9권1호
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• pp.19-24
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• 2023

최근 메모리 기술의 급격한 발전으로 개발되고 있는 다양한 종류의 메모리는 데이터 관리 시스템에서 처리 속도 향상을 위해 활용되고 있다. 특히 NAND 플래시 메모리는 전원이 차단되어도 데이터를 유지할 수 있는 비휘발성 특징이 있으므로 메모리 기반 저장장치의 데이터 저장용 주요 미디어로 활용되고 있다. 그러나 최근 연구되고 있는 메모리 기반 저장장치는 NAND 플래시 메모리뿐만 아니라 MRAM과 PRAM 등 다양한 종류의 메모리로 구성되어 있고 추가로 새로운 특성이 있는 다양한 종류의 메모리가 개발되고 있다. 따라서 특성이 서로 다른 이종의 메모리들로 구성된 저장 시스템에서 미디어의 데이터 처리 성능과 효율 향상을 위한 메모리 관리 기술의 연구가 필요하다. 본 논문에서는 데이터 관리를 위해 다양한 메모리로 구성된 저장장치에서 데이터를 효율적으로 관리하기 위한 메모리 사상 기법을 제안한다. 제안하는 아이디어는 서로 다른 이종 메모리를 하나의 사상 테이블을 활용하여 관리하는 방법이다. 이 방법은 데이터의 주소 체계를 통일할 수 있고 데이터 티어링(tiering)을 위해 서로 다른 메모리에 분할 저장된 데이터의 탐색 비용을 감소시킬 수 있다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.108-109
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• 2012

This talk will begin with the demonstration of facile synthesis of silicon nanostructures using the magnesiothermic reduction on silica nanostructures prepared via self-assembly, which will be followed by the characterization results of their performance for energy storage. This talk will also report the fabrication and characterization of highly porous, stretchable, and conductive polymer nanocomposites embedded with carbon nanotubes (CNTs) for application in flexible lithium-ion batteries. It will be presented that the porous CNT-embedded PDMS nanocomposites are capable of good electrochemical performance with mechanical flexibility, suggesting these nanocomposites could be outstanding anode candidates for use in flexible lithium-ion batteries. Directed self-assembly (DSA) of block copolymers (BCPs) can generate uniform and periodic patterns within guiding templates, and has been one of the promising nanofabrication methodologies for resolving the resolution limit of optical lithography. BCP self-assembly processing is scalable and of low cost, and is well-suited for integration with existing semiconductor manufacturing techniques. This talk will introduce recent research results (of my research group) on the self-assembly of Si-containing block copolymers for the achievement of sub-10 nm resolution, fast pattern generation, transfer-printing capability onto nonplanar substrates, and device applications for nonvolatile memories. An extraordinarily facile nanofabrication approach that enables sub-10 nm resolutions through the synergic combination of nanotransfer printing (nTP) and DSA of block copolymers is also introduced. This simple printing method can be applied on oxides, metals, polymers, and non-planar substrates without pretreatments. This talk will also report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by the self-assembly of Si-containing BCPs. This approach offers a practical pathway to fabricate high-density resistive memory devices without using high-cost lithography and pattern-transfer processes. Finally, this talk will present a novel approach that can relieve the power consumption issue of phase-change memories by incorporating a thin $SiO_x$ layer formed by BCP self-assembly, which locally blocks the contact between a heater electrode and a phase-change material and reduces the phase-change volume. The writing current decreases by 5 times (corresponding to a power reduction of 1/20) as the occupying area fraction of $SiO_x$ nanostructures varies.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.82-85
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• 1992

In this study, charge pumping method was used to investigate the Si-SiO$_2$interface characteristics of the nonvolatile SNOSFET memory devices, fabricated using the CMOS 1 Mbit processes (1.2$\mu\textrm{m}$ design rule), with thin oxide layer of 30${\AA}$ thick and nitride layer of 525${\AA}$ thick on the n-type silicon substrate (p-channel). Charge pumping current characteristics with the pulse base level were measured for various frequencies, falling times and rising times. By means of the charge dynamics in a non-steady state, the average Si-SiO$_2$interface state density and capture cross section were determined to be 3.565${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ and 4.834${\times}$10$\^$-16/$\textrm{cm}^2$, respectively. However Si-SiO$_2$ interface state densities were disributed 2.8${\times}$10$\^$-11/～5.6${\times}$10$\^$11/cm$\^$-2/～6${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ in the lover half of energy gap.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 춘계학술대회 논문집
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• pp.116-119
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• 1994

The characteristics of the Si-SiO$_2$ interface and the degradation in the short channel(L${\times}$W=1.7$\mu\textrm{m}$${\times}$15$\mu\textrm{m}$) SONOSFET nonvolatile memory devices, fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM with the 1.2$\mu\textrm{m}$ m design rule, were investigated using the charge pumping method. The SONOSFET memories have the tripple insulated-gate consisting of 30${\AA}$ tunneling oxide 205${\AA}$ nitride and 65${\AA}$ blocking oxide, The acceleration method which square voltage pulses of t$\_$p/=10msec, Vw=+19V and V$\_$E/=-22V continue to be alternatly applied to gale, was used to investigate the degradation of SONOSFET memories with the write/erase cycle. The degradation characteristics were ascertained by observing the change in the energy and spatial distributions of the interface trap density.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.35-35
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• 2003

Recent progress in the integration of the ferroelectric random access memories (FRAM) has attracted much interest. Strontium bismuth tantalate(SBT) is one of the most attractive materials for use in nonvolatile-memory applications due to low-voltage operations, low leakage current, and its excellent fatigue-free property. High-density FRAMs operated at a low voltage below 1.5V are applicable to mobile devices operated by battery. SBT films thinner than 0.1 #m can be operated at a low voltage, because the coercive voltage (Vc) decreases as the film thickness is reduced. In addition, the thickness of the SBT film will have to be reduced so it can fit between adjacent storage nodes in a pedestal type capacitor in future FRAMs.