• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2193-2198
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• 2016

In this study, we propose an algorithm to simulate the function of the coupling structure and having two neurons to find out exactly recover the temporary or permanent position errors that can occur during operation in a digital circuit was separated by function, a $3{\times}3$ array. If any particular part in the combined cells are differentiated cells have a problem that function to other cells caused an error and perform the same function are subjected to a step of apoptosis by the surrounding cells. Designed as a function block in the function and the internal structure having a cell structure of this digital circuit proposes an algorithm. In case of error of module 4 of block 1 considered in this study, sum of all module numbers for horizontal direction, total module number sum for vertical direction, and sum of all module numbers for diagonal direction, We were able to find the location.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.254-257
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• 1993

This paper presents a new method to implement Hebbian learning method on artificial neural network. In hebbian learning algorithm, complexity in terms of multiplications is high. To save the chip area, we consider a new learning circuit. By calculating similarity, or correlation between $X_i$ and $O_i$, large portion of circuits commonly used in conventional neural networks is not necessary for this new hebbian learning circuit named COR. The output signals of COR is applied to weight storage capacitors for direct control the voltages of the capacitors. The weighted sum, ${\Sigma}W_{ij}O_j$, is realized by multipliers, whose output currents are summed up in one line which goes to learning circuit or output circuit. The drain current of the multiplier can produce positive or negative synaptic weights. The pass transistor selects eight learning mode or recall mode. The layout of an learnable six-neuron fully connected Hopfield neural network is designed, and is simulated using PSPICE. The network memorizes, and retrieves the patterns correctly under the existence of minor noises.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.1-12
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• 2001

The adaptive learning circuit is designed on the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results are analyzed. The output frequency of the adaptive learning circuit is inversely proportional to the source-drain resistance of MFSFET and the capacitance of the circuit. The saturated drain current with input pulse number is analogous to the ferroelectric polarization reversal. It indicates that the ferroelectric polarization plays an important role in the drain current control of MFSFET. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of input pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristic of the adaptive learning circuit are confirmed. In other words, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed. Consequently it is shown that our circuit can be used effectively in the neuron synapses of nueral networks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.210-215
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• 2017

We have developed the neuromorphic system that can work with the four-terminal Si-based synaptic devices and verified the operation of the system using simulation tool and printed-circuit-board (PCB). The symmetrical current mirrors connected to the n-channel and p-channel synaptic devices constitute the synaptic integration part to express the excitation and the inhibition mechanism of neurons, respectively. The number and the weight of the synaptic devices affect the amount of the current reproduced from the current mirror. The double-stage inverters controlling delay time and the NMOS with large threshold voltage ($V_T$) constitute the action-potential generation part. The generated action-potential is transmitted to next neuron and simultaneously returned to the back gate of the synaptic device for changing its weight based on spike-timing-dependent-plasticity (STDP).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.534-540
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• 2008

The adaptive learning circuit is designed on the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results is analyzed. The output frequency of the adaptive learning circuit is inversely proportional to the source-drain resistance of MFSFET and the capacitance of the circuit. The saturated drain current with input pulse number is analogous to the ferroelectric polarization reversal. It indicates that the ferroelectric polarization plays an important role in the drain current control of MFSFET. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of input pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse, are confirmed. Consequently it is shown that our circuit can be used effectively in the neuron synapses of neural networks.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.37-50
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• 2007

In this paper, we designed and implementation of the high speed neuron processor for real time object recognition in the making automatic system. and we designed of the PE(Processing Element) used residue number system without carry propagation for the high speed operation. Consisting of MAC(Multiplication and Accumulation) operator using residue number system and sigmoid function operator unit using MAC(Mixed Radix conversion) is designed. The designed circuits are descript by C language and VHDL(Very High Speed Integrated Circuit Hardware Description Language) and synthesized by compass tools and finally, the designed processor is fabricated in $0.8{\mu}m$ CMOS process. we designed of MAC operation unit and sigmoid proceeding unit are proved that it could run time 0.6nsec on the simulation and improved to the speed of the three times and decreased to hardware size about 50%, each order. The designed neuron processor can be implemented of the object recognition in making automatic system with desired real time processing.

• Journal of The Korean Association of Information Education
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• v.24 no.6
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• pp.539-550
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• 2020

This study establishes the scientific basis for the use of digital learning materials through the education-neurological research method and derives implications for education based on education-neurological understandings. The main findings of the education-neurological analysis of digital learning materials are as follows: First, various sensory stimuli go through multiple sensory neurons and deep sections of the upper sphere and make possible the cooperative processing of information. Second, indirect experience from digital learning materials helps students understand the learning contents vividly through the mirror neuron system. Third, positive emotions originating from digital learning materials promote functions of dopamine, the reticular activating system, frontal-striatal circuit, cerebrum cortex. Based on the findings, the study suggests the following educational implications. First of all, when selecting digital learning materials, teachers should consider expression forms, learning contents, the flow of classes, and the adverse effects of digital learning materials. Next, it is effective to utilize digital learning materials in the lecture for provoking curiosity and enjoyment, maintaining interest and effort, and reviewing what students learned.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• Korean Journal of Computational Design and Engineering
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• v.2 no.1
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• pp.1-10
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• 1997

Finding the optimum route of ship's pipes is complicated and time-consuming process. Experience of designers is the main tool in this process. To reduce design man-hours and human errors a design expert system shell and a geometric modeler is used to automate the design process. In this paper, a framework of the intelligent CAD system for pipe auto-routing is suggested, which consists of general-purpose expert system shell and a geometric modeler. The design expert system and the geometric modeling kernel have been integrated. The CADDS5 of Computervision is used as the overall CAD environment. The Nexpert Object of Neuron Data is used as the expert system shell. The CADDS5 ISSM is used as the interface that creates and modifies geometric models of pipes. Existing algorithms for the routing problem have been analyzed. Most of them are to solve the 2-D circuit routing problems. Ship piping system, specially within the engine room, is a complicated, large scale 3-D routing problem. Methods of expert system have been used to find the route of ship pipes on the main deck.