• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.71-79
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• 1993

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.

• Molecules and Cells
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• v.41 no.5
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• pp.373-380
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• 2018

Synapses and neural circuits form with exquisite specificity during brain development to allow the precise and appropriate flow of neural information. Although this property of synapses and neural circuits has been extensively investigated for more than a century, molecular mechanisms underlying this property are only recently being unveiled. Recent studies highlight several classes of cell-surface proteins as organizing hubs in building structural and functional architectures of specific synapses and neural circuits. In the present minireview, we discuss recent findings on various synapse organizers that confer the distinct properties of specific synapse types and neural circuit architectures in mammalian brains, with a particular focus on the hippocampus and cerebellum.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.1033-1036
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• 1999

This paper proposes an efficient fault diagnosis for digital circuits using multilayer neural networks. The efficient learning algorithm is also proposed for the multilayer neural network, which is combined the steepest descent for high-speed optimization and the dynamic tunneling for global optimization. The fault-diagnosis system using the multilayer neural network of the proposed algorithm has been applied to the parity generator circuit. The simulation results shows that the proposed system is higher convergence speed and rate, in comparision with system using the backpropagation algorithm based on the gradient descent.

• ETRI Journal
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• v.31 no.2
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.70-81
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• 2002

This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pn-junction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and vMOS circuits.

• The Korean Journal of Physiology and Pharmacology
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• v.20 no.1
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• pp.1-8
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• 2016

Damage in the periphery or spinal cord induces maladaptive plastic changes along the somatosensory nervous system from the periphery to the cortex, often leading to chronic pain. Although the role of neural circuit remodeling and structural synaptic plasticity in the 'pain matrix' cortices in chronic pain has been thought as a secondary epiphenomenon to altered nociceptive signaling in the spinal cord, progress in whole brain imaging studies on human patients and animal models has suggested a possibility that plastic changes in cortical neural circuits may actively contribute to chronic pain symptoms. Furthermore, recent development in two-photon microscopy and fluorescence labeling techniques have enabled us to longitudinally trace the structural and functional changes in local circuits, single neurons and even individual synapses in the brain of living animals. These technical advances has started to reveal that cortical structural remodeling following tissue or nerve damage could rapidly occur within days, which are temporally correlated with functional plasticity of cortical circuits as well as the development and maintenance of chronic pain behavior, thereby modifying the previous concept that it takes much longer periods (e.g. months or years). In this review, we discuss the relation of neural circuit plasticity in the 'pain matrix' cortices, such as the anterior cingulate cortex, prefrontal cortex and primary somatosensory cortex, with chronic pain. We also introduce how to apply long-term in vivo two-photon imaging approaches for the study of pathophysiological mechanisms of chronic pain.

• ETRI Journal
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• v.30 no.4
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• pp.546-554
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• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.14-24
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• 2002

In this paper, a design of the pulsewidth-modulation(PWM) neural network with both retrieving and learning function is proposed. In the designed PWM neural system, the input and output signals of the neural network are represented by PWM signals. In neural network, the multiplication is one of the most commonly used operations. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Thus, the designed neural network only occupies the small chip area. By applying some circuit design techniques to reduce the nonideal effects, the designed circuits have good linearity and large dynamic range. Moreover, the delta learning rule can easily be realized. To demonstrate the learning capability of the realized PWM neural network, the delta learning nile is realized. The circuit with one neuron, three synapses, and the associated learning circuits has been designed. The HSPICE simulation results on the two learning examples on AND function and OR function have successfully verified the function correctness and performance of the designed neural network.

• Applied Microscopy
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• v.46 no.2
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• pp.100-104
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• 2016

Electron microscopy is currently the only available technique with a spatial resolution sufficient to identify fine neuronal processes and synaptic structures in densely packed neuropil. For large-scale volume reconstruction of neuronal connectivity, serial block-face scanning electron microscopy allows us to acquire thousands of serial images in an automated fashion and reconstruct neural circuits faster by reducing the alignment task. Here we introduce the whole reconstruction procedure of synaptic network in the rat hippocampal CA1 area and discuss technical issues to be resolved for improving image quality and segmentation. Compared to the serial section transmission electron microscopy, serial block-face scanning electron microscopy produced much reliable three-dimensional data sets and accelerated reconstruction by reducing the need of alignment and distortion adjustment. This approach will generate invaluable information on organizational features of our connectomes as well as diverse neurological disorders caused by synaptic impairments.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.62-71
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• 1994

A novel semiconductor device is proposed to be used as a processing element for the implementation of pulse-mode neural networks which consists of alternating n' GaAs quantum wells and undoped AlGaAs barriers sandwitched between n' GaAs cathode and P' GaAs anode and in simple circuit in conjunction with a parallel capacitive and resistive load the trigger circuit generates neuron-like pulse train output mimicking the function of axon hillock of biological neuron. It showed the sigmoidal relationship between the frequency of the pulse-train and the applied input DC voltage. In conjunction with MQWIMD the various neural circuits are proposed especially a neural chip monolithically integrated with photodetectors in order to perfrom the pattern recognition.