• Title/Summary/Keyword: network-on-chip

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FPGA integrated IEEE 802.15.4 ZigBee wireless sensor nodes performance for industrial plant monitoring and automation

  • Ompal, Ompal;Mishra, Vishnu Mohan;Kumar, Adesh
    • Nuclear Engineering and Technology
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    • v.54 no.7
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    • pp.2444-2452
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    • 2022
  • The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

Design of an FPGA-Based RTL-Level CAN IP Using Functional Simulation for FCC of a Small UAV System

  • Choe, Won Seop;Han, Dong In;Min, Chan Oh;Kim, Sang Man;Kim, Young Sik;Lee, Dae Woo;Lee, Ha-Joon
    • International Journal of Aeronautical and Space Sciences
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    • v.18 no.4
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    • pp.675-687
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    • 2017
  • In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

A Study on Realization of Visible Light Communication System for Power Line Communication Using 8-bit Microcontroller

  • Yun, Ji-Hun;Hong, Geun-Bin;Kim, Yong-Kab
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.5
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    • pp.238-241
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    • 2010
  • The purpose of this study is to solve the problems of radio frequency bandwidth frequency depletion, confusion possibilities, and security that are in current wireless communications systems, and to confirm the possibility of applying those solutions for the next generation network. To solve the problems of the current wireless communications system, a visible light communications system for power line communication (PLC) via 8-bit microcontroller is created and the capacity is analyzed. The exclusive PLC chip APLC-485MA, an 8-bit ATmega16 microcontroller, high brightness 5pi light emitting diodes (LEDs), and the LLS08-A1 visible light-receiving sensor were used for the transmitter and receiver. The performance was analyzed using a designed program and an oscilloscope. The voltage change was measured as a function of distance from 10-50 cm. Blue LEDs showed the best performance among the measured LED types, with 0.47 V of voltage loss, but for a distance over 50 cm, precise data was not easy to obtain due to the weak light. To overcome these types of problems, specific values such as the changing conditions and efficiency value relevant to the light emitting parts and the visible light-receiving sensor should be calculated, and continuous study and improvements should also be realized for better communication conditions.

Compact Hardware Multiple Input Multiple Output Channel Emulator for Wireless Local Area Network 802.11ac

  • Khai, Lam Duc;Tien, Tran Van
    • Journal of information and communication convergence engineering
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    • v.18 no.1
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    • pp.1-7
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    • 2020
  • This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

A Study on Realization and Receiving Characteristic Analysis of Visible Light Wireless Communication System for Power Line Communications Using ATmega16 Microcontroller (ATmega16 마이크로컨트롤러를 이용한 전력선통신용 가시광 무선통신 시스템 구현 및 수신 특성 분석)

  • Yun, Ji-Hun;Hong, Geun-Bin;Kim, Yong-Kab
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.11
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    • pp.2043-2047
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    • 2010
  • This study is to solve problems of depletion of RF bandwidth frequency, confusion possibility, security that current wireless communications system have and is to confirm possibility of applying next generation network. To solve problems of current wireless communications system, visible light communications system for power line communications using ATmega16 Microcontroller is was realized and receiver property was analyzed. PLC exclusive chip APLC-485MA, Microcontroller ATmega16, 5pi bulb type LED and high flux LED, visible light receiving sensor LLS08-A1 were used for transmitter and receiver. Performance was analyzed by designed program and an oscilloscope. It was showed average 20% improved receiver rate rather than bulb type LED in the case of high flux LED through voltage change rate on communication distance and LED type of distance between 10 to 50 cm. The blue LED showed the best performance among measured LED types with above 10% of voltage decreasing rate. But As it gradually becomes more distant, the precise date was difficult to obtain due to weak light. To overcome these sort of problems, specific values such as changing conditions and efficiency value relevant to light emitting parts and visible light receiving sensor should be calculated and continuous study and improvements should also be accomplished for the better communications condition.

A Study on Design of the Miniaturized Inverted-F Antenna Using Lumped Elements for Z-wave (집중소자를 이용한 Z-wave용 역 F형 안테나 소형화에 관한 연구)

  • Kwak, Min-Gil;Kim, Dong-Seek;Won, Young-Soo;Cho, Hyung-Rae
    • Journal of Advanced Marine Engineering and Technology
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    • v.33 no.8
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    • pp.1239-1245
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    • 2009
  • Currently, so many approaching methods are being developed to optimize the antenna size. In this paper, We fabricated Inverted-F type antenna attaching lumped components to solve the limitation of antenna size. Through experiments, a basic Inverted-F type antenna was fabricated and satisfied the adequate radiation pattern. After this, we researched the effect of antenna varied by matching circuit consist of chip type resistor, inductor, and capacitor. Using that elements, the antenna was matched at aim frequency. The proposed antenna's size is $7\;{\times}\;24\;mm$ that is very small size against the resonance frequence. Measuring the developed antenna, Its return loss was -18dB. Thus, this antenna can be used for Z-wave systems.

MMIC Cascade VCO with Low Phase Noise in InGaP/GaAs HBT Process for Ku-Band Application

  • Shrestha Bhanu;Lee Jae-Young;Lee Jeiyoung;Cheon Sang-Hoon;Kim Nam-Young
    • Journal of electromagnetic engineering and science
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    • v.4 no.4
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    • pp.156-161
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    • 2004
  • The MMIC cascode VCO is designed, fabricated, and measured for Ku-band Low Noise Blcok(LNB) system using InGaP/GaAs HBT technology. The phase noise of -116.4 dBc/Hz at 1 MHz offset with output power of 1.3 dBm is obtained at 11.526 GHz by applying 3 V and 11 mA, which is comparatively better characteristics than compared with the different configuration VCOs fabricated with other technologies. The simulated results of oscillation frequency and second harmonic suppression agree with the measured results. The phase noise is improved due to the use of the smallest value of inductor in frequency determining network and the InGaP ledge function of the technology. The chip size of $830\time781\;{\mu}m^2$ is also achieved.

A Small RFID Tag Antenna with Bandwidth-Enhanced Characteristic (대역폭 확장 특성을 갖는 소형 RFID 태그 안테나)

  • Lee Woo-Sung;Chang Ki-Hun;Yoon Young-Joong;Lee Byoung-Moo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.6 s.109
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    • pp.511-518
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    • 2006
  • In this paper, a small RFID tag antenna in UHF band which has bandwidth-enhanced characteristic is proposed. The shape of the proposed antenna is a meander antenna to have size-reduced characteristic, and it consists of two radiators which make dual resonance in adjacent frequency to enhance bandwidth. By adjusting length and location of each radiator, the proposed antenna can make dual resonance at arbitrary location on the Smith chart, which is able to make impedance matching with RFID tag chip in wide frequency range. And it is apparent that the proposed antenna can have bandwidth-enhanced characteristic according to the simulated and measured results.

A Novel 3-Level Transceiver using Multi Phase Modulation for High Bandwidth

  • Jung, Dae-Hee;Park, Jung-Hwan;Kim, Chan-Kyung;Kim, Chang-Hyun;Kim, Suki
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.791-794
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    • 2003
  • The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

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On-chip Smart Functions for Efficiency Enhancement of MMIC Power Amplifiers for W-CDMA Handset Applications

  • Youn S. Noh;Kim, Ji H.;Kim, Joon H.;Kim, Song G.;Park, Chul S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.1
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    • pp.47-54
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    • 2003
  • New efficiency enhancement techniques have been devised and implemented to InGaP/GaAs HBT MMIC power amplifiers for W-CDMA mobile terminals applications. Two different types of bias current control circuits that select the efficient quiescent currents in accordance with the required output power levels are proposed for overall power efficiency improvement. A dual chain power amplifier with single matching network composed of two different parallel-connected power amplifier is also introduced. With these efficiency enhancement techniques, the implemented MMIC power amplifiers presents power added efficiency (PAE) more than 14.8 % and adjacent channel leakage ratio(ACLR) lower than -39 dBc at 20 dBm output power and PAE more than 39.4% and ACLR lower than -33 dBc at 28 dBm output power. The average power usage efficiency of the power amplifier is improved by a factor of more than 1.415 with the bias current control circuits and even up to a factor of 3 with the dual chain power amplifier.