• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.18 no.1
• /
• pp.115-121
• /
• 2004

In this paper, a new distributed intelligent control module based on LonWoks fieldbus for air handling unit(AHU) of heating, ventilating and air-conditioning(HVAC) is proposed to replace with a conventional direct digital control(DDC) system with 32 bit microprocessor. The proposed control architecture has a excellent features such as highly compact and flexible function design, a low priced smart front-end and reliable performance with various functions. This also addresses issues in control network configuration, logical design of field devices by S/W tool, Internet networking and electronic element installation. Experimental results for showing the system performance are also included in this paper.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.2
• /
• pp.98-101
• /
• 2007

A fully integrated 5-GHz CMOS power amplifier for IEEE 802.11a WLAN applications is implemented using $0.18-{\mu}m$ CMOS technology. An on-chip transmission-line transformer is used for output matching network and voltage combining. Input balun, inter-stage matching components, output transmission line transformer and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier occupies a total area of $1.7mm{\times}1.2mm$. At a 3.3-V supply voltage, the amplifier exhibits a 22.6-dBm output 1-dB compression point, 23.8-dBm saturated output power, 25-dB power gain. The measured power added efficiency (PAE) is 20.1 % at max. peak, 18.8% at P1dB. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12dBm of average power at the EVM of -25dB.

• The KIPS Transactions:PartA
• /
• v.8A no.2
• /
• pp.147-156
• /
• 2001

A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

• Journal of electromagnetic engineering and science
• /
• v.9 no.1
• /
• pp.7-11
• /
• 2009

An Ultra-WideBand(UWB) Low-Noise Amplifier(LNA) is proposed and is implemented in a $0.18-{\mu}m$ CMOS technology. The proposed UWB LNA provides excellent wideband characteristics by combining a High-Pass Filter (HPF) with a conventional resistive-loaded LNA topology. In the proposed UWB LNA, the bell-shaped gain curve of the overall amplifier is much less dependent on the frequency response of the HPF embedded in the input stage. In addition, the adoption of fewer on-chip inductors in the input matching network permits a lower noise figure and a smaller chip area. Measurement results show a power gain of + 10 dB and an input return loss of more than - 9 dB over 2.7 to 6.2 GHz, a noise figure of 3.1 dB at 3.6 GHz and 7.8 dB at 6.2 GHz, an input PldB of - 12 dBm, and an IIP3 of - 0.2 dBm, while dissipating only 4.6 mA from a 1.8-V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.05a
• /
• pp.509-512
• /
• 2008

Ubiquitous Computing System란, 언제 어디서나 통신 및 컴퓨팅이 가능하고 컴퓨팅 시스템이 상호간에 정보를 공유하고 협력하는 컴퓨팅 시스템이다. 이로써 기존의 컴퓨팅 환경과 같이 사용자와 컴퓨터간의 대화형 상호작용이 아닌 물리적인 환경 상황(Context)등을 시스템이 스스로 인식하고 이를 기반으로 사용자와의 상호 작용을 지원하는 상황인식 기술이 필수적인 요소로 부각되고 있다. 또한, Ubiquitous Computing System을 위해 사용자 및 주변 환경 정보를 감지하는 센서(Sensor) 기술이 필요하다. 하지만 사용자 및 주변 환경으로부터 입력되는 불확실하거나 모호한 상황정보에 대한 표현과 추론에 대한 연구는 부족한 실정이다. 본 논문은 이런 이유에서 Rule-based System을 기반으로 CRS와 DOS의 개념을 도입한 새로운 상황인식 기반의 Architecture를 제안하고, 이를 VHDL을 통해 SoC로 구현하였다. CRS를 통해 실시간으로 다양한 센서에서 들어오는 많은 데이터에 가중치를 부여하여 각 센서마다 중요도를 달리 부여한다. 이로써, System은 Sensor 입력 값의 중요도에 따라 처리 순서를 우선적으로 부여하여 처리 속도를 높인다. 또, DOS를 통해 각양각색의 사용자에게 획일적인 서비스를 제공하는 것이 아니라 상황 변화의 패턴에 따라 개별화되고 특화된 서비스를 제공한다. 마지막으로, Ubiquitous Computing System의 향후 발전 가능성을 예상하고, 본 논문에서 제시한 Context-aware Architecture에 의해 구현된 UoC의 유용성을 짐작해 본다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.5A
• /
• pp.496-503
• /
• 2010

The implementation of a RF transceiver for WRAN(Wireless Regional Area Network) system based on IEEE 802.22 standard using Cognitive Radio technology is presented in this paper. A CMOS RF transceiver IC for WRAN system operates in VHF/UHF(54~862MHz) broadband, and employs dual-path direct-conversion configuration and the in-band harmonic distortions are effectively suppressed by exploiting the dual-path direct conversion architecture. For 64QAM(3/4 coding rate) OFDM signal, an EVM of <-31.4dB(2.7%) has been achieved at 10dBm off-chip PA output power and the total chip area with pads is 12.95 mm2. The experimental results show that the proposed CMOS RF transceiver IC has perfect performance for WRAN system based on TDD(Time Division Duplex) mode.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.9 no.2
• /
• pp.462-469
• /
• 2008

In this paper, we design the FPGA (Field-Programmable Gate Array) of the KOINONIA WPAN (Wireless Personal Area Network), and implement the SoC (System on Chip). We use the redundant bits to make a constant-amplitude in a modulator part. Additionally, the SNR (Signal to Noise Ratio) performance of the demodulator is improved by using the redundant bits in decoding steps. The four-million FPGA of the KOINONIA WPAN can be operated at 44MHz frequency. The PER (Packet Error Rate) of the designed FPGA with RF (Radio Frequency) module is below 1% at the -86dB MIPLS (Minimum Input Power Level Sensitivity), and the SNR is about 13dB. The SoC is implemented by using Hynix 0.25um CMOS (Complementary Metal Oxide Semiconductor) process. The size of the SoC is $6.52mm{\times}6.92mm$.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.34S no.12
• /
• pp.50-59
• /
• 1997

A wireless LAN medical information transmission system is useful for patients who need mobility in a local area environment. This paper proposes a method using WLAN(wireless local area network) and implements a stand-alone system with MAC(meidum access control) layer protocol referenced IEEE 802.11 draft standard. The system consists of a 8bit-microprocessor which handles media access control protocol and a WL100(GEC Plessey) chip which takes care of phsical layer specific routines and uses a RF module DE6003(GEC Plessey). The major features of the implemented system are the CSMA/CA protocol used a consecutive DATA-ACK trasmission method which yields more effective bandwidth allocation for asyncronous traffic transmission and the modified PCF protocol for time-bounded traffic transmission, which operates in ad-hoc network topology apart from IEEE 802.11 draft standard confirm PCF mode operate in infrastruture topology.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.10
• /
• pp.10-20
• /
• 1994

This paper presents a CATV SMS (Status Monitoring System) using HDLC (High Level Data Link Contorl) protocol and the system implementation.The system specifications were derived from the analysis of technical status and requirement of the domestic CATV industry. For the interoperability with a global network management system in the future, HDLC protocol was adopted in the system. The system performance was improved by using the communication controller chip and the large data buffer. For reducting the communication problems induced by accumulated noise in up-stream data channels, the system was designed that the different communication channel can be assigned to each proper mass of terminal. The operating software was designed with menu driven user interface and have various functions for the convenience of users. The test result of the implemented system at the experimental network showed good performance and suitability for a coaxial CATV Status Monitoring System.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.5
• /
• pp.451-458
• /
• 2013

This paper describes a design of LIN MCU using efficient memory accessing architecture which provides concurrent data and address fetch for faster communication. By using slew rate control it can reduce EMI emission while satisfying required communication specifications. To verify the efficiency of the LIN MCU, we developed a SoC and tested for several data packets. Measurements show that this LIN MCU improves network efficiency up to 17.19 % and response time up to 31.26 % for nominal cases. EMI radiation also can be reduced up to 10 dB.