• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.896-905
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• 2010

The sensor networks can be used attractively for various application areas. Time synchronization is important for any Ubiquitous Sensor Networks (USN) systems. USN makes extensive use of synchronized time in many contexts for data fusion. However existing time synchronization protocols are available only for homogeneous sensor nodes of USN. It needs to be extended or redesigned in order to apply to the USN with heterogeneous sensor nodes. Because heterogeneous sensor nodes have different clock sources with the SinkNode of USN, it is impossible to be synchronized global time. In addition, energy efficiency is one of the most significant factors to influence the design of sensor networks, as sensor nodes are limited in power, computational capacity, and memory. In this paper, we propose specific time synchronization based on master-slave topology for the global time synchronization of USN with heterogeneous sensor nodes. The time synchronization master nodes are always able to be synchronized with the SinkNode. Then time synchronization master nodes enable time synchronization slave nodes to be synchronized sleep periods. The proposed master-slave time synchronization for heterogeneous sensor nodes of USN is also helpful for power saving by maintaining maximum sleep time.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.831-833
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• 2004

In this paper, an obstacle avoidance algorithm is proposed for a network-based robot considering network delay by distribution. The proposed algorithm is based on the VFH(Vector Field Histogram) algorithm, and for the network-based robot system, in which it is assumed robot localization information is transmitted through network communication. In this paper, target vector for the VFH algorithm is estimated through the robot localization information and the measurement of its delay by distribution. The delay measurement is performed by time-stamp method. To synchronize all local clocks of the nodes distributed on the network, a global clock synchronization method is adopted. With the delay measurement, the robot localization estimation is performed by calculating the kinematics of the robot. The validation of the proposed algorithm is performed through the performance comparison of the obstacle avoidance between the proposed algorithm and the existing VFH algorithm on the network-based autonomous mobile robot.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2435-2437
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• 2004

In this paper, an obstacle avoidance algorithm is proposed for a network-based robot considering network delay by distribution. The proposed algorithm is based on the VFH(Vector Field Histogram) algorithm, and for the network-based robot system, in which it is assumed robot localization information is transmitted through network communication. In this paper, target vector for the VFH algorithm is estimated through the robot localization information and the measurement of its delay by distribution. The delay measurement is performed by time-stamp method. To synchronize all local clocks of the nodes distributed on the network, a global clock synchronization method is adopted. With the delay measurement, the robot localization estimation is performed by calculating the kinematics of the robot. The validation of the proposed algorithm is performed through the performance comparison of the obstacle avoidance between the proposed algorithm and the existing VFH algorithm on the network-based autonomous mobile robot.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.