• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.298-298
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• 2012

본 연구에서는 Bias Temperature Stress (BTS) 측정을 통한 다층세라믹커패시터(Multi-Layer Ceramic Capacitor, MLCC) 소자 분석에 대한 연구를 진행하였다. BTS 분석은 소자 내부에 존재하는 Na+, K+ 등의 mobile charge 검출을 위한 방법으로 positive bias와 negative bias stress에 따른 C-V 특성 곡선으로부터 mobile charge의 정량적 해석이 가능하다. 실험 결과 positive bias stress 후의 C-V 특성 곡선이 stress 전 C-V 특성 곡선과 비교해 negative bias 영역으로 0.0376 V 만큼 shift 하였다. 또한 수식(QM = $Cox{\cdot}{\triangle}V$)으로부터 $1.7{\times}1,011$개의 mobile charge가 존재함을 확인하였다. 본 연구는 MLCC 소자 내의 금속 오염물 존재 여부에 따른 소자의 전기적 특성 변화 분석을 위해 진행되었으며, BTS 분석은 반도체 소자 뿐 아니라 본 연구에서와 같이 커패시터 소자의 결함 여부 판단에도 이용 가능함을 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.340-341
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• 2012

In this work, we investigated the effects of temperature stress on flatband voltage (VFB) shifts of HfO2-SiO2 double gate dielectrics devices. Fig. 1 shows a high frequency C-V of the device when a positive bias for 10 min and a subsequent negative bias for 10 min were applied at room temperature (300 K). Fig. 2 shows the corresponding plot when the same positive and negative biases were applied at a higher temperature (473.15 K). These measurements are based on the BTS (bias temperature stress) about mobile charge in the gate oxides. These results indicate that the positive bias stress makes no difference, whereas the negative bias stress produces a significant difference; that is, the VFB value increased from ${\Delta}0.51$ V (300 K, Fig. 1) to ${\Delta}14.45$ V (473.15 K, Fig. 2). To explain these differences, we propose a mechanism on the basis of oxygen vacancy in HfO2. It is well-known that the oxygen vacancy in the p-type MOS-Cap is located within 1 eV below the bottom of the HfO2 conduction band (Fig. 3). In addition, this oxygen vacancy can easily trap the electron. When heated at 473.15 K, the electron is excited to a higher energy level from the original level (Fig. 4). As a result, the electron has sufficient energy to readily cross over the oxide barrier. The probability of trap about oxygen vacancy becomes very higher at 473.15 K, and therefore the VFB shift value becomes considerably larger.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.445-448
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• 2006

Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.

• 한국전기전자재료학회논문지
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• 제11권9호
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2013년도 춘계학술대회 논문집
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• pp.154-154
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• 2013

In this work, we investigated the characteristics and the effects of light on the negative gate bias stress stability (NBS) in high mobility polycrystalline IGO TFTs. IGO TFT showed a high drain current on/off ratio of ${\sim}10^9$, a field-effect mobility of $114cm^2/Vs$, a threshold voltage of -4V, and a subthresholdslpe(SS) of 0.28V/decade from log($I_{DS}$) vs $V_{GS}$. IGO TFTs showed large negative $V_{TH}$ shift(17V) at light power of $5mW/cm^2$ with negative gate bias stress of -10V for 10000seconds, at a fixed drain voltage ($V_{DS}$) of 0.5V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.266-269
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• 1997

Hot carrier effects as a function of bias stress time and bias stress conditions were syste-matica1ly investigated in p-channel po1y-Si TFT's fabricated on the quartz substrate. The device degradation was observed for the negative bias stress. After positive bias stressing, Improvement of electrical characteristic except for subthreshold slope was observed. It was found that these results were related to the hot carrier injection into the gate oxide and interface states at the poly-Si/SiO$_2$interface rather than defects states generation under bias stress.

• 한국표면공학회지
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• 제54권3호
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• pp.133-138
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• 2021

Ternary Ti-X-N coatings, where X = Al, Si, Cr, O, etc., have been widely used for machining tools and cutting tools such as inserts, end-mills, and etc. Ti-Al-N-O coatings were deposited onto silicon wafer and WC-Co substrates by a cathodic arc evaporation (CAE) technique at various negative substrate bias voltages. In this study, the influence of substrate bias voltages during deposition on the microstructure and mechanical properties of Ti-Al-N-O coatings were systematically investigated to optimize the CAE deposition condition. Based on results from various analyses, the Ti-Al-N-O coatings prepared at substrate bias voltage of -80 V in the process exhibited excellent mechanical properties with a higher compressive residual stress. The Ti-Al-N-O (-80 V) coating exhibited the highest hardness around 30 GPa and elastic modulus around 303 GPa. The improvement of mechanical properties with optimized bias voltage of -80 V can be explained with the diminution of macroparticles, film densification and residual stress induced by ion bombardment effect. However, the increasing bias voltage above -80 V caused reduction in film deposition rate in the Ti-Al-N-O coatings due to re-sputtering and ion bombardment phenomenon.

• 전기전자학회논문지
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• 제27권4호
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• pp.418-424
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• 2023

본 연구에서는 더블게이트 실리콘 나노시트 (SiNS) 피드백 전계효과 트랜지스터(FBFET)의 전기적 특성에 열처리가 미치는 영향을 분석하였다. 1000 초 동안 바이어스 스트레스를 인가했을 때 더블게이트 SiNS FBFET는 inversion layer의 전자에 의한 계면 트랩의 증가로 인해 채널 모드와 무관하게 negative bias stress 보다는 positive bias stress의 영향을 더 많이 받았다. 300 ℃에서 10 분 동안 열처리를 진행한 이후 소자는 원래의 특성을 완전히 회복하였으며 다시 1000 초 동안 바이어스 스트레스를 인가해도 특성이 변하지 않았다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.204.1-204.1
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• 2015

We studied the electrical properties and gate bias stress (GBS) stability of thin film transistors (TFTs) with multi-stacked InZnO layers. The InZnO TFTs were fabricated via solution process and the In:Zn molar ratio was 1:1. As the number of InZnO layers was increased, the mobility and the subthreshold swing (S.S) were improved, and the threshold voltage of TFT was reduced. The TFT with three-layered InZnO showed high mobility of $21.2cm^2/Vs$ and S.S of 0.54 V/decade compared the single-layered InZnO TFT with $4.6cm^2/Vs$ and 0.71 V/decade. The three-layered InZnO TFTs were relatively unstable under negative bias stress (NBS), but showed good stability under positive bias stress (PBS).

• 한국전기전자재료학회논문지
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• 제16권3호
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• pp.181-185
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• 2003

Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.