• Journal of Korean Port Research
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• v.15 no.1
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• pp.37-46
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• 2001

Fuzzy logic control(FLC) is composed of three parts : fuzzy rule-bases, membership functions, and scaling factors. Well-defined fuzzy rule-base should contain proper physical intuition on the plant, so are needed lots of experiences of the skillful expert. When membership functions are considered, some parameters on the memberships function such as function shape, support, allocation density should be selected well. The rule of scaling factors is 'scaling'(amplifying or reducing) for both input and output signals of the FLC to fit in the membership function support and to operate the plant intentionally. To get a better performance of the FLC, it is necessary to adjust the parameters of the FLC. In general, the adaptation of the scaling factors is the most effective adjustment scheme, compared with that of the fuzzy rule-base or membership function parameters. This study proposes the adaptation scheme of the scaling factors. When the adaptation is performed on-line, the stability of the adaptive FLC should be guaranteed. The stable FLC system can be designed with stability analysis in the sense of Lyapunov stability. To adapt the scaling factors for the error signals, the concept of the conventional MRAC would be introduced into slightly modified form. A tracking accuracy of the control system would be enhanced by the modified shape and support of the membership function. The simulation is achieved on the pilot plant with the hydraulic steering control of a UCT(Unmanned Container Transporter) of which modeling dynamics have lots of severe uncertainties and modeling errors.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.9
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• pp.114-129
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• 1996

This paper describes the whole development phase for the underwater vehicle actuating system with high hydroload torque disturbance. This includes requirement analysis, system modeling, control algorithm design, real time implementation, test and performance evaluations. As for driving control algorithms, fuzzy logic, variable structure and PD(Proportional-Differential) algorithm were designed and implemented on board controller using a single chip microprocessor. Intel 8797. And test and performance evaluation is carried out both single test and wystem integration test. We could confirm the basic performance of actuating system through the single test and gereral developing work of any actuating systems was finished with a single performance test of actuating system without system integration test. But, we suggested that system integration test be needed. System integration test is carried out using G/C HILS(Guidance and Control Hardware-In-the -Loop Simulation) which is constituted flight motion simulator, load simulator, real time host computer and the related subsystems such as inertial navigation system, power supply system and Guidance and Control Computer etc.. The most important practical contribution of this paper is that full system characteristics such as minimal control effort, enhancement of guidance and autopilot performance by the actuating system using G/C HILS technique are investigated. Through full running G/C HILS, in spite of the passing to single tests, some control algorithm resulted in failure as to stability of full system and system time frame.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}