• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.110-116
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• 1998

A single-crystalline epitaxial film of GaAs has been grown on Si using a gs assisted-ionized vapour beam eptaxial technique. The native oxide layer on the silicon substrate was removed at 550$^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high-temperature desorption. During the growth the substrate temperature was maintained at 550$^{\circ}C$. Transmission electron microscopy and electron diffraction data suggest that the GaAs layer is an epitaxially grown single-crystalline layer. The possibility of growing device quality GaAs on Si is able demonstrated through fabrication of GaAs MODFET on Si substrates.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.814-820
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• 1991

TaSi$_2$ was formed by rapid thermal annealing(RTA) on BF$_2$ doped single crystalline silicon substrates. The formation and various properties of TaSi$_2$ have been investigated by using 4-point probe, HP414, XRD, and SEM. And the redistribution of boron with RTA has been observed by SIMS. Implanted boron was diffused out into the TaSi$_2$ for RTA temperature but did not significantly affect the formation temperature of TaSi$_2$. Also, the contact resistance for TaSi$_2$/p$^{+}$ region had a low value 22$\Omega$, at contact size of 0.9$\mu$m, and the native oxide formed on Si-substrates by BF$_2$ implantation retarded the formation of TaSi$_2$.

• Journal of the Korean Vacuum Society
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• v.12 no.S1
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• pp.83-87
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• 2003

Zirconium oxide films have been synthesized by radio-frequency magnetron sputtering deposition on n-Si(001) substrate with metal zirconium target at variant $O_2$ partial pressures. The influences of $O_2$ partial pressures of the morphology, deposition rate, microstructure, and the dielectric constant of $ZrO_2$ have been discussed. The results show that deposition rate of $ZrO_2$ films decreases, the roughness, and the thickness of the native $SiO_2$ interlayer increases with the increase of $O_2$ partial pressure. $ZrO_2$ films synthesized at low $O_2$ partial pressure are amorphous and monoclinic polycrystalline in nanometer scale at low $O_2$ partial pressure. The relative dielectrics of $ZrO_2$ films are in the range of 12 to 25.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.106-108
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• 1994

Electromigration(EM) tests were carried out on Al and Cu films in HV systems to study surface migration. The Al films were made on oxidized silicon wafers by thermal evaporation, in-situ annealed at 300$^{\circ}C$, patterned, and EM tested at 260$^{\circ}C$ and 4.5MA/$\textrm{cm}^2$. SEM observation with back scattered electron mode on the EM tested Al films disclosed that thinning took place under the native Al oxide. In the case of Cu films, tested using in-situ TEM, thinning was also observed at the early stage of void formation even though the thinned areas were much less than those of the Al films.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.250-253
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• 1990

A single-crystalline epitaxial film of GaAs has been grown on Si using an ionized cluster beam technique. The native oxide layer on the silicon substrate was removed at $550^{\circ}C$ by use of an accelerated arsonic ion beam, instead of a high-temperature desorption. During the growth the substrate temperature was maintained at $550^{\circ}C$. Transmission electron microscopy and electron diffraction data suggest that the eats layer is an epitaxially grown single-crystalline layer.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• Journal of the Optical Society of Korea
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• v.19 no.3
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• pp.217-221
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• 2015

Developing a metallization that has low cost and high efficiency is essential in solar-cell industries, to replace expensive silver-based metallization. Ni/Cu two-step metallization is one way to reduce the cost of solar cells, because the price of copper is about 100 times less than that of silver. Alkaline electroless plating was used for depositing nickel seed layers on the front electrode area. Prior to the nickel deposition process, 2% HF solution was used to remove native oxide, which disturbs uniform nickel plating. In the subsequent step, a nickel sintering process was carried out in $N_2$ gas atmosphere; however, copper was plated by light-induced plating (LIP). Plated nickel has different properties under different bath conditions because nickel electroless plating is a completely chemical process. In this paper, plating bath conditions such as pH and temperature were varied, and the metal layer's structure was analyzed to investigate the adhesion of Ni/Cu metallization. Average adhesion values in the range of 0.2-0.49 N/mm were achieved for samples with no nickel sintering process.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.422-448
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• 1996

Low-temperature epitaxial growth of Si and SiGe layers of Si is one of the important processes for the fabrication of the high-speed Si-based heterostructure devices such as heterojunction bipolar transistors. Low-temperature growth ensures the abrupt compositional and doping concentration profiles for future novel devices. Especially in SiGe epitaxy, low-temperature growth is a prerequisite for two-dimensional growth mode for the growth of thin, uniform layers. UHV-ECRCVD is a new growth technique for Si and SiGe epilayers and it is possible to grow epilayers at even lower temperatures than conventional CVD's. SiH and GeH and dopant gases are dissociated by an ECR plasma in an ultrahigh vacuum growth chamber. In situ hydrogen plasma cleaning of the Si native oxide before the epitaxial growth is successfully developed in UHV-ECRCVD. Structural quality of the epilayers are examined by reflection high energy electron diffraction, transmission electron microscopy, Nomarski microscope and atomic force microscope. Device-quality Si and SiGe epilayers are successfully grown at temperatures lower than 600℃ after proper optimization of process parameters such as temperature, total pressure, partial pressures of input gases, plasma power, and substrate dc bias. Dopant incorporation and activation for B in Si and SiGe are studied by secondary ion mass spectrometry and spreading resistance profilometry. Silicon p-n homojunction diodes are fabricated from in situ doped Si layers. I-V characteristics of the diodes shows that the ideality factor is 1.2, implying that the low-temperature silicon epilayers grown by UHV-ECRCVD is truly of device-quality.

• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.99-102
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• 2004

Display process has adopted RCA clean, being applied to large area and coped with environmental issue for last ten years. However, the approaching concept of ozonized, hydrogenised, or electrolyzed water cleaning technologies is within RCA clean paradigm. In this work, only electrolyzed anode water was applied to clean particles and organics as well as metals based on Pourbaix concept, and as a test vehicle, MgO particles were introduced to prove the new concept. The electrolyzed anode water is very oxidative with high oxidation reduction potential(ORP) and low in pH of more than 900mV and 3.1, respectively. MgO particles were immerged in the anode water and its weight losses due to dissolution were measured with time. Weight losses were in the ranges of 100 to 500 micrograms in 250m1 anode waters depending on their ORP and pH. Therefore it was concluded that the cleaning radicals in the anode water was at least in the range of 1 to 5E20 ea per 250 ml anode water equivalent to IE18 ea/cm3. Hence it can be assumed that the anode water be applied to display cleaning since 1E10 to IE15 ea/cm3 ranges of contaminants are being treated. In addition, it was observed that anode water does not develop micro-roughness on hydrophobic surface while it does on the native silicon oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.399-399
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• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.