• Korean Journal of Optics and Photonics
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• v.22 no.6
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• pp.269-275
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• 2011

We propose a metal-dielectric hybrid waveguide structure consisting of a single metal nanowire placed on a flat dielectric slab. Mode size and propagation loss of the surface-plasmons confined in the metal-dielectric gap are compared with those of the complementary structure with a dielectric nanowire on a metal surface. In the case of the nanowire's diameter much smaller than the wavelength the two structures reveal quite different characteristics; the dielectric nanowire-on-metal has longer propagation distance, but only the metal nanowire-on-dielectric exhibits a mode size two fold smaller than the diffraction limit. The proposed hybrid structure may therefore be more suitable for realization of nanocavity lasers.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.501-504
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• 2014

Si nanowire는 트랜지스터, 배터리 등 광범위한 응용이 가능한 물질로서 이의 효율적 활용을 위해서는 그 다양한 구조에 대한 물성 변화의 연구가 중요하다. 이 연구에서는 [110] 방향의 $4{\times}3$, $6{\times}4$, $8{\times}5$ Si nanowire에 대하여 DFT 기반 제일원리적 계산을 수행함으로써, $6{\sim}14{\AA}$ 범위에서 nanowire 지름의 변화에 따른 전자구조 의존성에 대하여 연구하였다. 그 결과, bulk와 비교하여 Si nanowire의 경우 bandwidth 감소 및 bandgap의 증가가 나타나며, 이러한 경향은 nanowire 지름이 커질수록 점진적으로 약화됨을 알 수 있었다.

• Journal of Electrical Engineering and Technology
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• v.7 no.3
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• pp.396-400
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• 2012

Novel fabrication method of nanobridge array of various materials was proposed using suspended silicon nanowire array as a sacrificial template structure. Nanobridges of various materials can be simply fabricated by direct deposition with thermal evaporation on the top of prefabricated suspended silicon nanobridge arrays, which are used as a sacrificial structure. Since silicon nanowire can be easily removed by selective dry etching, nanobridge arrays of an intended material are finally obtained. In this paper, metal nanobridges of Ti/Au, around 50-200 nm in thickness and width, 5-20 ${\mu}m$ in length were fabricated to prove the advantages of the proposed nanowire or nanobridge fabrication method. The nanobridges of Ti/Au after complete removal of sacrificial silicon nanowire template were well-established and bending of nanobridge caused by the tensile stress was observed after silicon removing. Up to 50 nm and 10 ${\mu}m$ of silicon nanowire in diameter and length respectively was also very useful for nanowire templates.

• Korean Journal of Materials Research
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• v.20 no.1
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• pp.25-30
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• 2010

Si nanowire/multiwalled carbon nanotube nanocomposite arrays were synthesized. Vertically aligned Si nanowire arrays were fabricated by Ag nanodendrite-assisted wet chemical etching of n-type wafers using $HF/AgNO_3$ solution. The composite structure was synthesized by formation of a sheath of carbon multilayers on a Si nanowire template surface through a thermal CVD process under various conditions. The results of Raman spectroscopy, scanning electron microscopy, and high resolution transmission electron microcopy demonstrate that the obtained nanocomposite has a Si nanowire core/carbon nanotube shell structure. The remarkable feature of the proposed method is that the vertically aligned Si nanowire was encapsulated with a multiwalled carbon nanotube without metal catalysts, which is important for nanodevice fabrication. It can be expected that the introduction of Si nanowires into multiwalled carbon nanotubes may significantly alter their electronic and mechanical properties, and may even result in some unexpected material properties. The proposed method possesses great potential for fabricating other semiconductor/CNT nanocomposites.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.30.2-30.2
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• 2010

Nano-scale p-n junction can generate various nano-scale functional devices such as nanowire light emitting diode, nanowire solar cell, and nanowire sensor. The core shell type nanowire p-n junction has been considered for the high efficient devices in many previous reports. On the other hand, although device efficiency is relatively lower, the cross bar type p-n junction has simple topological structure, suggested by C.M. Lieber group, to integrate easily many p-n junction devices in one board. In this study, for the integration of the cross bar nanowire p-n junction device, a simple fabrication route, employed dielectrophoretic array and direct printing techniques, was demonstrated by the successful fabrication and programmable integration of the nanowire cross bar p-n junction solar cell. This direct printing process will give the single nanowire solar cell the opportunity of the integration on the circuit board with other nanowire functional devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.47-47
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• 2009

The formation of variable one-dimensional structures including core/shell structure is of particular significance with respect to potential applications for thermoelectric devices with the enhanced figure of merit ($ZT=S2{\sigma}T/{\kappa}$). We report the fabrication of Bi-Te core/shell nanowire based on a novel stress induced method. Fig. 1 schematically shows the nanowire fabrication process. Bi nanowires are grown on the Si substrate by the stress-induced method, and then Te is evaporated on the Bi nanowires. Fig. 2 is a transmission electron microscopy image clearly showing a core/shell structure for which effective phonon scattering and quantum confinement effect are expected. Electrical conductivity of the core/shell nanowire was measured at the temperatures from 4K to 300K, respectively. Our results demonstrate that Bi-Te core/shell nanowire can be grown successfully by the stress-induced method. Based on the result of electrical transport measurement and characteristic morphology of rough surface, Seebeck coefficient and thermal conductivity of Bi-Te core/shell nanowires are presented.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1896-1901
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• 2008

Single crystalline copper nanowires are subjected to bending tests using molecular dynamics simulations and the embedded atom method. To observe behaviors of nanowire, bending tests are performed for various rates of deflection and different boundary conditions: fixed-free and fixed-fixed. When the deflection of nanowire becomes large, twinnings and dislocations appear, and <100> crystal structure transforms to <110>. At high rates, phase transformation occurs in whole nanowire. But, at low rates, atomic structure changes to <110> phase partially. The final deformed structures are affected by the rate of deflection and boundary conditions. These effects can be important design parameters at nanoscale.

• Journal of the Optical Society of Korea
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• v.12 no.2
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• pp.65-68
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• 2008

The miniband structure of a quantum dot lattice based on GaN/AlN nanowire arrays has been investigated using the finite element method and Floquet theorem. The quantum dot modes and the quantum wire modes in the nanowire arrays were graphically verified. The optimum geometries of GaN/AlN quantum wire arrays were investigated by using a correlation between the width of nanowires and the separation of the minibandgap which is to be larger than the thermal energy at room temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.560-560
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• 2012

We report a one-step fabrication method of Poly(9,9-dioctylfluorene) (PFO) nanowire array with pronounced ${\beta}$-Phase. We use liquid-bridge-mediated nanotransfer molding (LB-nTM) which is a new direct nano-patterning method based on the direct transfer of various materials from a mold to a substrate via liquid layer. The formation of the ${\beta}$-phase morphology in the resulting PFO nanowire array was evidenced by the presence of an absorption peak at 435nm. With the collection polarizer oriented parallel to the wire long axis, the PL emission was most intense and an emission dichroic ratio, DRE, of 3.7 was determined. The nanowire array have been investigated by scanning electron microscopy (SEM). Also, we simply fabricated structure of device of ITO/PFO nanowire arrays/Al and the electroluminescence spectra were recorded at various applied voltage.

• Transactions on Electrical and Electronic Materials
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• v.13 no.2
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• pp.73-77
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• 2012

Operation of liquid crystal displays (LCDs) can be improved by monolithic integration of the pixel transistors with light emitting diodes (LEDs) on a single substrate. Conventional LCDs make use of filters to control the backlighting which reduces the overall efficiency. These LCDs also utilize LEDs in series which impose failure and they require high voltage for operation with a power factor correction. The screen of small hand-held devices can operate from moderate brightness. Therefore, III-V nanowires that are grown along with transistors over Silicon substrates can be utilized. Control of nanowire LEDs with nanowire transistors will significantly lower the cost, increase the efficiency, improve the manufacturing yield and simplify the structure of the small displays that are used in portable devices. The steps to grow nanowires on Silicon substrates are described. The vertical n-type and p-type nanowire transistors with surrounding gate structures are characterized. While biased at 0.5 V, nanowire transistors with minimum radius or channel width have an OFF current which is less than 1pA, an ON current more than 1 ${\mu}A$, a total delay less than 10 ps and a transconductance gain of more than 10 ${\mu}A/V$. The low power and fast switching characteristics of the nanowire transistor make them an ideal choice for the realization of future displays of portable devices with long battery lifetime.