• Journal of the Korean Vacuum Society
• /
• v.14 no.1
• /
• pp.40-48
• /
• 2005

Bucky shuttle memory systems were investigated by the classical molecular dynamics(MD) simulations. Energetics and operating response of the shuttle-memory-elements u?ere examined by MD simulations of the C/sub 60/ shuttle in the nanomemory systems under various external force fields. Single-nanopeapod type was consisting of three fullerenes encapsulated in (10, 10) boron-nitride nanotube and filled Cu electrode. Studied systems could be applied to nonvolatile memory. MD simulation results showed that the stable bit flops could be achieved from the external force fields of 0.1 eV/Å for single-nanopeapod type.

• Journal of Sensor Science and Technology
• /
• v.16 no.4
• /
• pp.313-318
• /
• 2007

Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

• Transactions on Electrical and Electronic Materials
• /
• v.11 no.3
• /
• pp.93-105
• /
• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.29 no.9
• /
• pp.571-575
• /
• 2016

Recently, there has been much focus on the controlled alignment and patterning process of nanowires for nanoelectronic devices. A simple and effective method for patterning of highly aligned nanowires using a microcontact printing technique is demonstrated. In this method, nanowires are first directionally aligned by contact printing, following which line and space micropatterns of nanowire arrays are accomplished by microcontact printing with a micro patterned NOA mold.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.644-644
• /
• 2013

Graphene is a two-dimensional sp2 layer material. Despite the short history in the empirical synthesis of the graphene layers, the academic/industrial unique features have brought highly significant interest in research and development related to graphene-related materials. In particular, the electrical and optical performances have been targeted towards pre-existing microelectronicand emerging nanoelectronic applications. The graphene synthesis relies on a variety of processing factors, such as temperature, pressure, and gas ratios involving H2, CH4, and Ar, in addition to the inherent selection of copper substrates. The current work places its emphasis on the role of experimental factors in growing graphene thin films. The thermally-grown graphene layers are characterized using physical/chemical analyses, i.e., four point resistance measurements, Raman spectroscopy, and UV-Visible spectrophotometry. Ultimately, an optimization strategy is proposed in growing high-quality graphene layers well-controlled through empirical factors.

• Advances in nano research
• /
• v.5 no.1
• /
• pp.61-67
• /
• 2017

A semi-empirical approach to model the temperature effects on I-V characteristics of Carbon Nanotube Field Effect Transistors (CNTFETs) is proposed. The model includes two thermal parameters describing CNTFET behaviour in terms of saturation drain current and threshold voltage, whose values are extracted from the simulated and trans-characteristics of the device in different temperature conditions. Our results are compared with those of a numerical model online available, obtaining I-V characteristics comparable but with a lower CPU calculation time.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2011.05a
• /
• pp.19.2-19.2
• /
• 2011

ZnO nanowires have been fabricated by vapor-liquid-solidification with hot-walled pulsed laser deposition method. The diameter of ZnO nanowire has been systematically controlled simply by changing the thickness of Au catalyst. Field effect transistors with different diameter have been fabricated by using photolithography and e-beam lithography. The threshold voltage of ZnO nanowire FET showed enhanced mode and depleted mode depending on the diameter of ZnO nanowires. This is mainly due to the change of the carrier concentration depending on the size of nanowires. We have fabricated ZnO nanowire inverters using nanowire FETs. This simple method to fabricate ZnO nano-inverter will be useful to open the possibility of ZnO nanoelectronic applications.

• Electronics and Telecommunications Trends
• /
• v.20 no.5 s.95
• /
• pp.28-45
• /
• 2005

무어의 법칙을 근간으로 하는 전계효과 트랜지스터는 매 18개월마다 0.7배씩의 성공적인 소형화를 거듭하여 최근에는 50nm 크기로 구성된 약 1억 개의 트랜지스터가 집적된 칩을 생산하고 있다. 그러나 트랜지스터의 크기가 50nm 이하로 줄어들면서는 단순한 소형화 과정은 근본적인 물리적인 한계에 접근하게 되었다. 특히 게이트 절연막의최소 두께는 트랜지스터의 소형화에 가장 직접적인 중요한 요소이나, 실리콘 산화막의 두께가 2nm 이하가 되면서 게이트 절연막을 집적 터널링하는 전자에 의한 누설전류의 급격한 증가로 인하여 그 사용이 어려워지고 있는 추세이다. 따라서 본 논문에서는 트랜지스터의 소형화에 악영향을 미치는 물리적인 한계요소에 대하여 살펴보고, 이러한 소형화의 한계를 뛰어넘기 위한 노력의 일환으로 연구되고 있는 이중게이트 구조의 트랜지스터, 쇼트키 트랜지스터, 나노선을 이용한 트랜지스터 및 분자소자 등의 새로운 소자구도에 대하여 살펴보고자 한다.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.575-575
• /
• 2012

Synthesis of novel two dimensional materials has gained tremendous attention recently as they are considered as alternative materials for replacing graphene that suffers from a lack of bandgap, a property that is essential for many applications. Single layer molybdenum disulfide ($MoS_2$) has a direct bandgap (1.8eV) that is promising for use in next-generation optoelectronics and energy harvesting devices. We have successfully grown high quality single layer $MoS_2$ by a facile vapor-solid transport route. As-grown single layer $MoS_2$ was carefully characterized by using X-ray diffraction, Raman spectroscopy, field emission scanning electron microscopy and electrical transport measurement. The results indicate that a high quality single layer $MoS_2$ can be successfully grown on silicon substrate. This may open up great opportunities for the exploration of novel nanoelectronic devices.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.1049-1052
• /
• 2007

Extremely sharp and uniform Transfer Mold FEAs with thin film low work function TiN emitter material have been fabricated by controlling the thickness of the coated emitter materials to realize high efficient, high reliable and low-cost vacuum nanoelectronic devices..Their tip radii are 8.3-13.8 nm. Turn-on electric fields of the Ni FEAs and TiN-FEAs resulted in the low electric field values of $31.6\;V/{\mu}m$ and $44.2V/{\mu}m$,respectively, at the short emitter/anode distance: less than $30\;{\mu}m$, which are lower than those of conventional FE As such as Spindt type FEAs and carbon nan otube FEAs The Transfer Metal Mold fabrication method is one of the best methods of changing emit ter materials with sharp and uniform emit ter shapes.