• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.19.2-19.2
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• 2011

ZnO nanowires have been fabricated by vapor-liquid-solidification with hot-walled pulsed laser deposition method. The diameter of ZnO nanowire has been systematically controlled simply by changing the thickness of Au catalyst. Field effect transistors with different diameter have been fabricated by using photolithography and e-beam lithography. The threshold voltage of ZnO nanowire FET showed enhanced mode and depleted mode depending on the diameter of ZnO nanowires. This is mainly due to the change of the carrier concentration depending on the size of nanowires. We have fabricated ZnO nanowire inverters using nanowire FETs. This simple method to fabricate ZnO nano-inverter will be useful to open the possibility of ZnO nanoelectronic applications.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.314-319
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• 2014

Here, we review the various methods for the preparation of vanadium dioxide ($VO_2$) films and nanowires, and their potential applications to the sensors such as gas sensor, strain sensor, and temperature sensor. $VO_2$ is an interesting material on account of its easily accessible and sharp Mott metal-insulator transition (MIT) at ${\sim}68^{\circ}C$ in the bulk. The MIT is also triggered by the electric field, stress, magnetic field etc. This paper involves exceptionally sensitive hydrogen sensors based on the catalytic process between hydrogen molecules and Pd nanoparticles on the $VO_2$ surface, and fast responsive sensors based on the self-heating effects which leads to the phase changes of the $VO_2$. These features will be seen in this paper and can enable strategies for the integration of a $VO_2$ material in advanced and complex functional units such as logic gates, memory, FETs for micro/nano-systems as well as the sensors.

• Korean Journal of Materials Research
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• v.26 no.11
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• pp.635-643
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• 2016

Graphene has shown exceptional properties for high performance devices due to its high carrier mobility. Of particular interest is the potential use of graphene nanoribbons as field-effect transistors. Herein, we introduce a facile approach to the fabrication of graphene nanoribbon (GNR) arrays with ~200 nm width using nanoimprint lithography (NIL), which is a simple and robust method for patterning with high fidelity over a large area. To realize a 2D material-based device, we integrated the graphene nanoribbon arrays in field effect transistors (GNR-FETs) using conventional lithography and metallization on highly-doped $Si/SiO_2$ substrate. Consequently, we observed an enhancement of the performance of the GNR-transistors compared to that of the micro-ribbon graphene transistors. Besides this, using a transfer printing process on a flexible polymeric substrate, we demonstrated graphene-silicon junction structures that use CVD grown graphene as flexible electrodes for Si based transistors.

• Advances in nano research
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• v.10 no.1
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• pp.91-99
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• 2021

Silicene is an emerging two-dimensional (2D) semiconductor material which has been envisaged to be compatible with conventional silicon technology. This paper presents a theoretical study of uniformly doped silicene with aluminium (AlSi3) Field-Effect Transistor (FET) along with the benchmark of device performance metrics with other 2D materials. The simulations are carried out by employing nearest neighbour tight-binding approach and top-of-the-barrier ballistic nanotransistor model. Further investigations on the effects of the operating temperature and oxide thickness to the device performance metrics of AlSi3 FET are also discussed. The simulation results demonstrate that the proposed AlSi3 FET can achieve on-to-off current ratio up to the order of seven and subthreshold swing of 67.6 mV/dec within the ballistic performance limit at room temperature. The simulation results of AlSi3 FET are benchmarked with FETs based on other competitive 2D materials such as silicene, graphene, phosphorene and molybdenum disulphide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.4
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• pp.285-296
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• 2005

Reduced pressure chemical vapor deposition technology has been used to study SiGe heterostructure epitaxy and device issues, including SiGe relaxed buffers, proper control of Ge component and crystalline defects, two dimensional delta doping, and their influence on electrical properties of devices. From experiments, 2D profiles of B and P presented FWHM of 5 nm and 20 nm, respectively, and doses in 5×10/sup 11/ ∼ 3×10/sup 14/ ㎝/sup -2/ range. The results could be employed to fabricate SiGe/Si heterostructure field effect transistors with both Schottky contact and MOS structure for gate electrodes. I-V characteristics of 2D P-doped HFETs revealed normal behavior except the detrimental effect of crystalline defects created at SiGe/Si interfaces due to stress relaxation. On the contrary, sharp B-doping technology resulted in significant improvement in DC performance by 20-30 ％ in transconductance and short channel effect of SiGe HMOS. High peak concentration and mobility in 2D-doped SiGe heterostructures accompanied by remarkable improvements of electrical property illustrate feasible use for nano-sale FETs and integrated circuits for radio frequency wireless communication in particular.