• Title/Summary/Keyword: nano scale CMOSFETs

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Thermal Stability Improvement of Ni-Silicide on the SOI Substrate Doped B11 for Nano-scale CMOSFET (나노급 CMOSFET을 위한 SOI기판에 Doping된 B11을 이용한 Ni-Silicide의 열안정성 개선)

  • Jung, Soon-Yen;Oh, Soon-Young;Kim, Yong-Jin;Lee, Won-Jae;Zhang, Ying-Ying;Zhong, Zhun;Li, Shi-Guang;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.24-25
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    • 2006

  • In this study, Ni silicide on the SOI substrate doped B11 is proposed to improve thermal stability. The sheet resistance of Ni-silicide utilizing pure SOI substrate increased after the post-silicidation annealing at $600^{\circ}C$ for 30 min. However, using the proposed B11 implanted substrate, the sheet resistance showed stable characteristics after the post-silicidation annealing up to $700^{\circ}C$ for 30 min.

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The Study of Ni-Pd Alloy Characteristics to Form a NiSi for Shallow S/D Junction (Shallow S/D Junction에 적용 가능한 NiSi를 형성하기 위한 Ni-Pd 합금의 특성 연구)

  • Lee, Won-Jae;Oh, Soon-Young;Agchbayar, Tuya;Yun, Jang-Gn;Kim, Yong-Jin;Zhang, Ying-Ying;Zhong, Zhun;Kim, Do-Woo;Cha, Han-Seob;Heo, Sang-Bum;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.603-606
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    • 2005

  • In this paper, the formation and thermal stability of Ni-silicide using Ni-Pd alloys is studied for ultra shallow S/D junction of nano-scale CMOSFETs. There are no different effects when Ni-Pd is used in single structure and TiN capping structure. But, in case of Cobalt interlayer structure, it was found that Pure Ni had lower sheet resistance than Ni-Pd, because of a thick silicide. Also, Ni-Pd has merits that surface of silicide and interface between silicide and silicon have a good morphology characteristics. As a result, Ni-Pd is an optimal candidate for shallow S/D junction when cobalt is used for thermal stability.

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Dependence of Analog and Digital Performance on Carrier Direction in Strained-Si PMOSFET (Strained-Si PMOSFET에서 디지털 및 아날로그 성능의 캐리어 방향성에 대한 의존성)

  • Han, In-Shik;Bok, Jung-Deuk;Kwon, Hyuk-Min;Park, Sang-Uk;Jung, Yi-Jung;Shin, Hong-Sik;Yang, Seung-Dong;Lee, Ga-Won;Lee, Hi-Deok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.8
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    • pp.23-28
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    • 2010

  • In this paper, comparative analysis of digital and analog performances of strained-silicon PMOSFETs with different carrier direction were performed. ID.SAT vs. ID.OFF and output resistance, Rout performances of devices with <100> carrier direction were better than those of <110> direction due to the greater carrier mobility of <100> channel direction. However, on the contrary, NBTI reliability and device matching characteristics of device with <100> carrier direction were worse than those with <110> carrier direction. Therefore, simultaneous consideration of analog and reliability characteristics as well as DC device performance is highly necessary when developing mobility enhancement technology using the different carrier direction for nano-scale CMOSFETs.

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