• Journal of Korean Vacuum Science & Technology
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• 제4권1호
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• pp.11-17
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• 2000

The low temperature electron mobilities were investigated in Si/$Si_{1-x}Ge_{x}$ modulation Doped (MOD) quantum well structure with thermally grown oxide. N-type Si/$Si_{1-x}Ge_{x}$ structures were fabricated by a gas source MBE. Thermal oxidation was carried out in a dry $O_2$ atmosphere at $700^{\circ}C$ for 7 hours. Electron mobilities were measured by a Hall effect and a magnetoresistant effect at low temperatures down to 0.4 K. Pronounced Shubnikov-de Haas (SdH) oscillations were observed at a low temperature showing two dimensional electron gases (2 DEG) in a tensile strained Si quantum well. The electron sheet density ($n_{s}$) of 1.5${\times}$$10^{12}$[$cm^{-2}$] and corresponding electron mobility of 14200 [$cm^2$$V^{-1}$$s^{-1}$] were obtained at low temperature of 0.4 K from Si/$Si_{1-x}Ge_{x}$ MOD quantum well structure with thermally grown oxide.

• 센서학회지
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• 제21권4호
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• pp.283-286
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• 2012

This paper presents the optical hydrogen sensor based on transparent 3C-SiC membrane and photovoltaic effect. Gasochromic materials of Pd and Pd/$WO_3$ were deposited by sputter on 3C-SiC membrane for gas sensing area. Gasochromic materials change to transparency by exposure to hydrogen. The variations of light intensity by hydrogen generate the photovoltaic of P-N junction between N-type 3C-SiC and P-type Si. Single layer of Pd shows higher photovoltaic compared with Pd/$WO_3$. However, phase transition from ${\alpha}$ to ${\beta}$ is shown at 6 %. Pd/$WO_3$ structure show the more linear response to hydrogen range of 2 % ~10 %. Also, almost 2 times fast response and recovery characteristics are shown at Pd/$WO_3$. These fast performances are come from the fact that Pd promoted the chemical reaction between hydrogen and $WO_3$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1760-1762
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• 2000

본 논문은 기존의 $Si_{3}N_4$, SiN 물질 대신 Pt를 사용해 HF 용액속에서 다공질 실리콘과 전극을 동시에 형성하는 기술을 개발하였다. Pt를 실리콘 웨이퍼 위에 직접 증착한 후 습식 에칭과 Lift-off 공정을 사용하여 Pt를 패터닝하였다. 습식 에칭은 에칭용액의 온도를 일정하게 유지하는 것이 중요하며, 증착한 Pt 박막이 BOE 에칭에 견디고, Lift-off 공정이 가능하기 위해서는 기판온도를 l100$^{\circ}C$ 이하로 해야한다. Pt를 사용하면 기존의 mask에서 발생하는 가장자리 부분에서의 전류 집중이 방지되기 때문에 다공질 실리콘이 일정한 깊이로 형성되고, Al대신 오믹 전극으로 사용할 수 있다. 현재 Pt를 mask와 전극으로 이용한 P-I-N UV detector, 광 바이오센서, 습도센서 제작등에 응용 연구가 진행되고 있다.

• 대한기계학회논문집
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• 제18권9호
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• pp.2374-2385
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• 1994

SiCw/Al composite material is especially attractive because of their superior specific strength, specific stiffness, corrosion fatigue resistance, creep resistance, and wear resistance compared with the corresponding wrought Al alloy. In this study, Fatigue crack growth behavior and fatigue crack path morphology(FCPM) of SiC whisker reinforced Al 6061 alloy with 25% SiC volume fraction and Al 6061 allay were performed. Result of the fatigue crack growth test sgiwed that fatigue crack growth rate of SiCw/Al 6061 composite was slower than that of Al 6061 matrix therefore it was confirmed that Sic whisker have a excellent fatigue resistance. And Al 6061 matrix had only FCPM perpendicular to loading direction. On the other hand SiCw/Al 6061 composite had three types in fatigue crack path morphology. First type is that both sides FCPM of artificial notch are perpendicular to loading direction. Second type is that a FCPM in artifical notch has slant angle to loading direction and the other side FCPM is perpendicular to loading direction. Third type is that both sides FCPM of notch have slant angle to loading direction. It was considered that this kinds of phenomena were due to non-uniform distribution of SiC whisker and confirmed by SEM observation for fracture mechanism study.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.278-278
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• 2009

A photovoltaic device consisting of arrays of radial p-n junction wires enables a decoupling of the requirements for light absorption and carrier extraction into orthogonal spatial directions. Each individual p-n junction wire in the cell is long in the direction of incident light, allowing for effective light absorption, but thin in orthogonal direction, allowing for effective carrier collection. To fabricate radial p-n junction solar cells, p or n-type vertical Si wire cores need to be produced. The majority of Si wires are produced by the vapor-liquid-solid (VLS) method. But contamination of the Si wires by metallic impurities such as Au, which is used for metal catalyst in the VLS technique, results in reduction of conversion efficiency of solar cells. To overcome impurity issue, top-down methods like noble metal catalytic etching is an excellent candidate. We used noble metal catalytic etching methods to make Si wire arrays. The used noble metal is two; Au and Pt. The method is noble metal deposition on photolithographycally defined Si surface by sputtering and then etching in various BOE and $H_2O_2$ solutions. The Si substrates were p-type ($10{\sim}20ohm{\cdot}cm$). The areas that noble metal was not deposited due to photo resist covering were not etched in noble metal catalytic etching. The Si wires of several tens of ${\mu}m$ in height were formed in uncovered areas by photo resist. The side surface of Si wires was very rough. When the distance of Si wires is longer than diameter of that Si nanowires are formed between Si wires. Theses Si nanowires can be removed by immersing the specimen in KOH solution. The optimum noble metal thickness exists for Si wires fabrication. The thicker or the thinner noble metal than the optimum thickness could not show well defined Si wire arrays. The solution composition observed in the highest etching rate was BOE(16.3ml)/$H_2O_2$(0.44M) in Au assisted chemical etching method. The morphology difference was compared between Au and Pt metal assisted chemical etching. The efficiencies of radial p-n junction solar Cells made of the Si wire arrays were also measured.

• 한국결정성장학회지
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• 제19권4호
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• pp.159-164
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• 2009

실리콘 기판에 GaN 에피성장을 확인하기 위해, P형 Si(100), Si(111) 기판 전면에 버퍼층으로 40 nm 두께의 코발트실리사이드를 형성시켰다. 형성된 코발트실리사이드 층에 연속으로 HVPE(hydride vapor phase epitaxy)로 하나는 $850^{\circ}C$-12분 + $1080^{\circ}C$-30분(공정I)과, 또 하나 조건은 $557^{\circ}C$-5분 + $900^{\circ}C$-5분(공정II) 조건으로 각각 나누어 진행하여 보았다. GaN의 에피성장을 광학현미경, 주사전자현미경, 주사탐침현미경, 그리고 HR-XRD로 확인하였다. 공정I로는 GaN의 에피성장이 진행되지 않았으며, 공정II에서는 에피성장이 진행되었다. 특히 공정 II는 열팽창에 의해 실리콘 기판과의 자가정렬적인 기판분리 현상을 보였으며, XRD로 GaN의 0002 방향의 결정성 (crystallinity)을 ${\omega}$-scan으로 확인한 결과(100)면 방향의\ 실리콘과 코발트실리사이드를 버퍼층으로 활용하고 저온에서 HVPE를 진행한 조합이 GaN의 에피성장에 유리하였다.

• 대한전자공학회논문지
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• 제26권6호
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• pp.30-37
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• 1989

Silane($SiH_4$), methane($CH_4$), diborane(B_2H_6)그리고 phosphine($PH_3$)을 이용하여 rf글로방전분해법으로 PIN형 a-SiC:H/a-Si:H 이종접합 태양전지를 제작하였다. $SnO_2/ITO$층 형성치 태양전지의 효율은 ITO 투명전극만의 경우보다 1.5% 향상되었다. 제작조건은 P층의 경우 $CH_4/SiH_4$의 비를 5로 하고 두께는 $100{\AA}$이었다. I층은 P층위에 증착하였으나 진성이 아니고 N형에 가깝다. 이 I층을 진성으로 바꾸기 위해서 0.3ppm의 $B_2H_6$를 $SiH_4$에 혼합하여 5000${\AA}$증착했다. 또한 N층은 $PH_4/SiH_4$의 비를 $10^{-2}$로 하여 $400{\AA}$ 증착시켰다. 그 결과 입사강도가 15mW/$cm^2$일 때 개방전압 $V_{oc}=O'$단락전류밀도 $J_{sc=14.6mA/cm^2}$, 충진율 FF=58.2%, 그리고 효율 ${eta}=8.0%$를 나타내었다. 빛의 반사에 의한 손실을 감소시키기 위하여 $MgF_2$를 유리기판위에 도포하였다. 이에 의한 효율은 0.5% 향상되어 전체적인 효율은 8.5%였다.

• Applied Science and Convergence Technology
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• 제24권3호
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• pp.53-59
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• 2015

The field-effect transistors (FETs) with a graphene-based p-n junction channel were fabricated using the patterned self-assembled monolayers (SAMs). The self-assembled 3-aminopropyltriethoxysilane (APTES) monolayer deposited on $SiO_2$/Si substrate was patterned by hydrogen plasma using selective coating poly-methylmethacrylate (PMMA) as mask. The APTES-SAMS on the $SiO_2$ surface were patterned using selective coating of PMMA. The APTES-SAMs of the region uncovered with PMMA was removed by hydrogen plasma. The graphene synthesized by thermal chemical vapor deposition was transferred onto the patterned APTES-SAM/$SiO_2$ substrate. Both p-type and n-type graphene on the patterned SAM/$SiO_2$ substrate were fabricated. The graphene-based p-n junction was studied using Raman spectroscopy and X-ray photoelectron spectroscopy. To implement low voltage operation device, via ionic liquid ($BmimPF_6$) gate dielectric material, graphene-based p-n junction field effect transistors was fabricated, showing two significant separated Dirac points as a signature for formation of a p-n junction in the graphene channel.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.18-19
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• 2008

Polycrystalline(poly) 3C-SiC film is a promising structural material for M/NEMS used in harsh environments, bio and fields. In order to realize poly 3C-SiC based M/NEMS devices, the electrical properties of poly 3C-SiC film have to be optimized. The n-type poly 3C-SiC thin film is deposited by APCVD using HMDS$(Si_2(CH_3)_6)$ as single precursor and are in-situ doped using N2. Resistivity values as low as 0.014 $\Omega$cm were achieved. The carrier concentration increased with doping from $3.0819\times10^{17}$ to $2.2994\times10^{19}cm^{-3}$ and electronicmobility increased from 2.433 to 29.299 $cm^2/V{\cdot}s$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.129-130
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• 2008

Polycrystalline silicon (poly-Si) Schottky barrier thin film transistors (SB-TFT) are fabricated by erbium silicided source/drain for n-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs have a large on/off current ratio with a low leakage current. Moreover, the electrical characteristics of poly-Si SB TFTs are significantly improved by the additional forming gas annealing in 2 % $H_2/N_2$, because the interface trap states at the poly-Si grain boundaries and at the gate oxide/poly-Si channel decreased.