• Title/Summary/Keyword: n/i buffer layer

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Study on New LIGBT with Multi Gate for High Speed and Improving Latch up Effect (래치 업 특성의 개선과 고속 스위칭 특성을 위한 다중 게이트 구조의 새로운 LIGBT)

  • 강이구;성만영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.5
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    • pp.371-375
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    • 2000
  • In this paper a new conductivity modulated power transistor called the Lateral Insulated Gated Bipolar Transistor which included n+ ring and p-channel gate is presented. A new lateral IGBT structure is proposed to suppress latch-up and to improve turn off time by imploying n+ ring and p-channel gate and verified by MEDICI. The simulated I-V characteristics at $V_{G}$=15V show that the latch up occurs at $V_{A}$=18V and 6.9$\times$10$^{-5}$ A/${\mu}{\textrm}{m}$ for the proposed LIGBT while the conventional LIGBT latches at $V_{A}$=1.3V and 1.96${\mu}{\textrm}{m}$10$^{-5A}$${\mu}{\textrm}{m}$. It is shown that turn off characteristic of new LIGBT is 8 times than that of conventional LIGBT. And noble LIGBT is not n+ buffer layer because that It includes p channel gate and n+ ring. Therefore Mask for the buffer layer isn’t needed. The concentration of n+ ring is and the numbers of n+ ring and p channel gate are three for the optimal design.n.n.n.n.

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The Study of Different Buffer Structure on Ni-W Tape for SmBCO Coated Conductor

  • Kim, T.H.;Kim, H.S.;Oh, S.S.;Ko, R.K.;Ha, D.W.;Song, K.J.;Lee, N.J.;Yang, J.S.;Jung, Y.H.;Youm, D.J.;Park, K.C.
    • Progress in Superconductivity and Cryogenics
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    • v.8 no.4
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    • pp.8-11
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    • 2006
  • High temperature superconducting coated conductor has various buffer structures on Ni-W alloy. We comparatively studied the growth conditions of a multi buffer layer $(CeO_2/YSZ/CeO_2)$ and a single buffer layer$(CeO_2)$ on textured Ni-W alloy tapes. XRD data showed that the qualities of in-plane and out-of-plane textures of the two type buffer structures were good. Also, we investigated the properties of SmBCO superconducting layer that was deposited on the two type buffer structure. The SmBCO superconducting properties on the single and multi buffer structure showed different critical current values and surface morphologies. FWHM of In-plane and out-of-plane textures were $7.4^{\circ},\;5.0^{\circ}$ in the top CeO2 layer of the multi-buffer layers of $CeO_2/YSZ/CeO_2$, and $7.3^{\circ},\;5.1^{\circ}$ in the $CeO_2$ single buffer layer. $1{\mu}m-thick$ SmBCO superconducting layers were deposited on two type buffer layer. $I_c$ of SmBCO deposited on single and multi buffer were 90 A/cm, 150 A/cm and corresponding $J_c$ were $0.9MA/cm^2,\;1.5MA/cm^2$ at 77K in self-field, respectively.

Hard TiN Coating by Magnetron-ICP P $I^3$D

  • Nikiforov, S.A.;Kim, G.H.;Rim, G.H.;Urm, K.W.;Lee, S.H.
    • Journal of the Korean institute of surface engineering
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    • v.34 no.5
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    • pp.414-420
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    • 2001
  • A 30-kV plasma immersion ion implantation setup (P $I^3$) has been equipped with a self-developed 6'-magnetron to perform hard coatings with enhanced adhesion by P $I^3$D(P $I^3$ assisted deposition) process. Using ICP source with immersed Ti antenna and reactive magnetron sputtering of Ti target in $N_2$/Ar ambient gas mixture, the TiN films were prepared on Si substrates at different pulse bias and ion-to-atom arrival ratio ( $J_{i}$ $J_{Me}$ ). Prior to TiN film formation the nitrogen implantation was performed followed by deposition of Ti buffer layer under A $r^{+}$ irradiation. Films grown at $J_{i}$ $J_{Me}$ =0.003 and $V_{pulse}$=-20kV showed columnar grain morphology and (200) preferred orientation while those prepared at $J_{i}$ $J_{Me}$ =0.08 and $V_{pulse}$=-5 kV had dense and eqiaxed structure with (111) and (220) main peaks. X-ray diffraction patterns revealed some amount of $Ti_{x}$ $N_{y}$ in the films. The maximum microhardness of $H_{v}$ =35 GN/ $M^2$ was at the pulse bias of -5 kV. The P $I^3$D technique was applied to enhance wear properties of commercial tools of HSS (SKH51) and WC-Co alloy (P30). The specimens were 25-kV PII nitrogen implanted to the dose 4.10$^{17}$ c $m^{-2}$ and then coated with 4-$\mu\textrm{m}$ TiN film on $Ti_{x}$ $N_{y}$ buffer layer. Wear resistance was compared by measuring weight loss under sliding test (6-mm $Al_2$ $O_3$ counter ball, 500-gf applied load). After 30000 cycles at 500 rpm the untreated P30 specimen lost 3.10$^{-4}$ g, and HSS specimens lost 9.10$^{-4}$ g after 40000 cycles while quite zero losses were demonstrated by TiN coated specimens.s.

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Improved Carrier Tunneling and Recombination in Tandem Solar Cell with p-type Nanocrystalline Si Intermediate Layer

  • Park, Jinjoo;Kim, Sangho;Phong, Pham duy;Lee, Sunwha;Yi, Junsin
    • Current Photovoltaic Research
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    • v.8 no.1
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    • pp.6-11
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    • 2020
  • The power conversion efficiency (PCE) of a two-terminal tandem solar cell depends upon the tunnel-recombination junction (TRJ) between the top and bottom sub-cells. An optimized TRJ in a tandem cell helps improve its open-circuit voltage (Voc), short-circuit current density (Jsc), fill factor (FF), and efficiency (PCE). One of the parameters that affect the TRJ is the buffer layer thickness. Therefore, we investigated various TRJs by varying the thickness of the buffer or intermediate layer (TRJ-buffer) in between the highly doped p-type and n-type layers of the TRJ. The TRJ-buffer layer was p-type nc-Si:H, with a doping of 0.06%, an activation energy (Ea) of 43 meV, an optical gap (Eg) of 2.04 eV, and its thickness was varied from 0 nm to 125 nm. The tandem solar cells we investigated were a combination of a heterojunction with intrinsic thin layer (HIT) bottom sub-cell and an a-Si:H (amorphous silicon) top sub-cell. The initial cell efficiency without the TRJ buffer was 7.65% while with an optimized buffer layer, its efficiency improved to 11.74%, i.e., an improvement in efficiency by a factor of 1.53.

Effect of a-SiOx Buffer Layer in the Thin Film Silicon Solar Cell (a-SiOx Buffer Layer 삽입을 통한 고효율 비정질 실리콘 박막태양전지에 관한 및 연구)

  • Park, Seung-Man;Lee, Sun-Hwa;Kong, Dae-Young;Lee, Wan-Back;Jung, Wu-Wan;Yi, Jun-Sin
    • 한국신재생에너지학회:학술대회논문집
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    • 2009.11a
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    • pp.386-386
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    • 2009
  • TCO/p/i/n 구조의 비정질 실리콘 박막 태양전지의 제작에 있어서 TCO계면과 p층사이의 이종접합에서의 큰 밴드갭 차이는 p층으로부터의 정공 재결합을 통하여 효율 저하의 원인이 된다. 이러한 재결합은 넓은 밴드갭을 가진 물질을 완충층으로 삽입함으로써 개선되어 질 수 있다. 본 논문에서는 비정질 실리콘 보다 넓은 광학적 밴드갭을 가지는 a-SiOx 박막을 완충층으로 사용하여 TCO/P 계면에서의 재결합 감소에 대한 시뮬레이션을 수행하였다. a-SiOX 박막 내에 포함된 산소의 양에 따라 밴드갭을 조절하여 1.8eV~2.0eV 사이의 완충층을 삽입하여 박막태양전지의 개방전압, 단락전류, 효율 등에 끼치는 영향을 ASA 시뮬레이션을 통하여 알아보았다.

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${\mu}c$-Si window layer를 이용한 박막 태양전지의 고효율화에 관한 simulation

  • Park, Seung-Man;Gong, Dae-Yeong;Lee, Jun-Sin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.403-403
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    • 2011
  • TCO/p/i/n 구조의 비정질 실리콘 박막 태양전지의 제작에 있어서 a-Si 혹은 넓은 밴드갭 물질인 SiOx, SiC 등은 window layer로 주로 사용 되어왔다. 그러나 ${\mu}c$-Si는 우수한 광학적, 전기적 특성에 불구하고 낮은 activation energy에 의한 p/i interface 에서의 band-off set에 의한 정공재결합에 의해 사용되어 지지 못했다. 이러한 재결합은 p/i interface상에 buffer layer를 삽입함으로써 개선되어 질 수 있다. 본 논문에서는 비정질 실리콘 보다 넓은 광학적 밴드갭을 가지는 a-SiOx 박막을 완충층으로 사용하여 p/i 계면에서의 재결합 감소에 대한 시뮬레이션을 수행하였다. a-SiOX 박막 내에 포함 된 산소의 양에 따라 밴드갭을 조절하여 1.8eV~2.0eV 사이의 완충층을 삽입하여 박막태양전지의 개방전압, 단락전류, 효율 등에 끼치는 영향을 ASA 시뮬레이션을 통하여 알아보았다.

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Improvement of Hybrid EL Efficiency in Nanoparticle EL Devices by Insertion of the Layers of PVK and BaF2

  • Lee, Jun-Woo;Cho, Kyoung-Ah;Kim, Hyun-Suk;Park, Byoung-Jun;Kim, Sang-Sig;Kim, Sung-Hyun
    • Transactions on Electrical and Electronic Materials
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    • v.6 no.3
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    • pp.101-105
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    • 2005
  • Electroluminescence(EL) and current-voltage(I-V) characteristics of hybrid EL devices containing Pr and Mn co-doped ZnS nanoparticles were investigated in this study. For the insertion of a hole transport layer of poly (N-vinyl carbazole)(PVK), the current level became lower due to the accumulation of electrons at the interface between PVK and nanoparticles. When both PVK and buffer layer $BaF_2$ were simultaneously introduced, the enhanced EL efficiency and improved I-V characteristics were obtained. This results from the additional increase of hole injection owing to the internal field induced by the significant accumulation of electrons at the interface. The presence of buffer layer $BaF_2$ together with PVK makes it possible the charge accumulation enough to induce the sufficient internal field for further hole injection.

buffer layer 삽입을 통한 TCO/p interface 특성에 관한 simulation 및 분석

  • Park, Seung-Man;Gong, Dae-Yeong;Lee, Jun-Sin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.340-340
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    • 2011
  • TCO/p/i/n 구조의 비정질 실리콘 박막 태양전지의 제작에 있어서 TCO계면과 p층사이의 이종 접합에서의 큰 밴드갭 차이는 p층으로부터의 정공 재결합을 통하여 효율 저하의 원인이 된다. 이러한 재결합은 넓은 밴드갭을 가진 물질을 완충층으로 삽입함으로써 개선되어 질 수 있다. 본 논문에서는 비정질 실리콘 보다 넓은 광학적 밴드갭을 가지는 a-SiOx 박막을 완충층으로 사용하여 TCO/P 계면에서의 재결합 감소에 대한 시뮬레이션을 수행하였다. a-SiOX 박막 내에 포함된 산소의 양에 따라 밴드갭을 조절하여 1.8eV~2.0eV 사이의 완충층을 삽입하여 박막태양 전지의 개방전압, 단락전류, 효율 등에 끼치는 영향을 ASA 시뮬레이션을 통하여 알아보았다.

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Magnetoresistance of Buffer/CoFe/Cu/Co Sandwiches (Buffer 층을 갖는 CoFe/ Cu/ Co 샌드위치 박막의 자기저항 특성)

  • 송은영;오미영;김경민;이장로;김미양;김희중;박창만;이상석;황도근
    • Journal of the Korean Magnetics Society
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    • v.7 no.3
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    • pp.146-151
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    • 1997
  • Buffer (t $\AA$)/ CoFe(35$\AA$)/Cu (50$\AA$)/Co (35$\AA$) sandwiches prepared by dc magnetron sputtering on Corning glass substrates using the $Co_{90}Fe_{10}$ and Co layers with different coercivities. Dependence of magnetoresistance on the type and thickness of buffer layers, and on the thickness of Cu and the magnetic layers in buffer/ CoFe/Cu /Co sandwiches were investigated. Magnetoresistance ratio and saturation field $H_s$ increased as thickness of the buffer layer becomes thicker, then decreased smoothly after a maximum value. An improved filed sensitivity was realized with the $Ni_{81}Fe_{19}$ buffer layer.

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Fabrication of a Depletion mode n-channel GaAs MOSFET using $Al_2O_3$ as a gate insulator ($Al_2O_3$ 절연막을 게이트 절연막으로 이용한 공핍형 n-채널 GaAs MOSFET의 제조)

  • Jun, Bon-Keun;Lee, Suk-Hyun;Lee, Jung-Hee;Lee, Yong-Hyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.1
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    • pp.1-7
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    • 2000
  • In this paper, we present n-channel GaAs MOSFET having $Al_2O_3$ as gate in insulator fabricated on a semi-insulating GaAs substrate. 1 ${\mu}$m thick undoped GaAs buffer layer, 1500 ${\AA}$ thick n-type GaAs, undoped 500 ${\AA}$ thick AlAs layer, and 50 ${\AA}$ GaAs caplayer were subsequently grown by molecular beam epitaxy(MBE) on (100) oriented semi-insulating GaAs substrate oxidized. When it was wet oxidized, AlAs layer was fully converted $Al_2O_3$. The I-V, $g_m$, breakdown charateristics of the fabricated GaAs MOSFET showed that wet thermal oxidation of AlAs/GaAs epilayer/S${\cdot}$I GaAs was suitable in realizing depletion mode GaAs MOSFET.

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