• Journal of the Korean Institute of Telematics and Electronics
• /
• v.2 no.2
• /
• pp.9-16
• /
• 1965

The characteristics of electronic multipliers and their accuracy are analyzed. From the analysis a low cost, four-quadrant timedivision electronic multiplier jis built. This multiplier produces an output voltage equal to 0.01 of the instantaneous product of two input voltage representing independent variables. Each input may either be constant or vary with time over a range of ${\pm}$100 volts. Drift and noise in this multiplier are kept at very low level and dynamic response is below 0.5 decibels up to 700 cycles per second. Methods of testing this multiplier and the results are also described. It is shown that the results agree with theoretical values satisfactorily.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.28B no.10
• /
• pp.799-806
• /
• 1991

Utilizing dual basis, normal basis, and subfield representation, three different finite field multipliers are presented in this paper. First, we propose an extended dual basis multiplier based on Berlekamp's bit-serial multiplication algorithm. Second, a detailed explanation and design of the Massey-Omura multiplier based on a normal basis representation is described. Third, the multiplication algorithm over GF(($2^{n}$) utilizing subfield is proposed. Especially, three different multipliers are designed over the finite field GF(($2^{4}$) and the complexity of each multiplier is compared with that of others. As a result of comparison, we recognize that the extendd dual basis multiplier requires the smallest number of gates, whereas the subfield multiplier, due to its regularity, simplicity, and modularlity, is easier to implement than the others with respect to higher($m{\ge}8$) order and m/2 subfield order.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.1
• /
• pp.928-930
• /
• 2005

With an increasing importance of the information security issues, the efficienct calculation process in terms of finite field level is becoming more important in the Elliptic curve cryptosystems. Serial multiplication architectures are based on the Mastrovito's serial multiplier structure. In this paper, we manipulate the numerical expressions so that we could suggest a 3-times as fast as (3x) the Mastrovito's multiplier using the polynomial basis. The architecture was implemented with HDL, to be evaluated and verified with EDA tools. The implemented 3x GF (Galois Field) multiplier showed 3 times calculation speed as fast as the Mastrovito's, only with the additional partial-sum generation processing unit.

• Bulletin of the Korean Mathematical Society
• /
• v.58 no.2
• /
• pp.461-479
• /
• 2021

This paper includes a general version of Bessel multipliers in Hilbert C∗-modules. In fact, by combining analysis, an operator on the standard Hilbert C∗-module and synthesis, we reach so-called generalized Bessel multipliers. Because of their importance for applications, we are interested to determine cases when generalized multipliers are invertible. We investigate some necessary or sufficient conditions for the invertibility of such operators and also we look at which perturbation of parameters preserve the invertibility of them. Subsequently, our attention is on how to express the inverse of an invertible generalized frame multiplier as a multiplier. In fact, we show that for all frames, the inverse of any invertible frame multiplier with an invertible symbol can always be represented as a multiplier with an invertible symbol and appropriate dual frames of the given ones.

• Journal of Advanced Navigation Technology
• /
• v.14 no.3
• /
• pp.391-396
• /
• 2010

This paper presents some important research result comparisons for multi function RF modules which use amplifier or frequency multiplier. By using multiplier, multi function module can be realized amply in comparison to multi band module which has separate block for each frequency band. Some com paring analysis among the switching method between separate amplifier and multiplier, the structure using frequency selective reflector, and the module using the defected ground structure. The multi function module which operates as amplifier or multiplier with input frequency is developed and input frequency suppression and output harmonics suppression can be improve d by using defected ground structure.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.67-72
• /
• 2013

A low-power bypassing Booth multiplier for mobile multimedia applications is proposed. The bypassing structure directly transfers input values to outputs without switching the internal nodes of a multiplier, enabling low-power design. The proposed Booth multiplier adopts the bypassing structure while the bypassing is usually adopted in the Braun multipliers. Simulation results show the proposed Booth multiplier achieves an 11% reduction in terms of the proposed FoM compared to prior works.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.3
• /
• pp.145-151
• /
• 2003

This study focuses on the hardware implementation of fast and low-complexity multiplier over GF(2$^{m}$ ). Finite field multiplication can be realized in two steps: polynomial multiplication and modular reduction using the irreducible polynomial and we will treat both operation, separately. Polynomial multiplicative operation in this Paper is based on the Permestzi's algorithm, and irreducible polynomial is defined AOP. The realization of the proposed GF(2$^{m}$ ) multipleker-based multiplier scheme is compared to existing multiplier designs in terms of circuit complexity and operation delay time. Proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.

• Journal of KIISE:Computer Systems and Theory
• /
• v.33 no.4
• /
• pp.223-230
• /
• 2006

The method of implementing a modular multiplier for Montgomery multiplication by using an adder depends on a selected adder. When using a CPA, there is a carry propagation problem. When using a CSA, it needs an additional calculation for a final result. The Multiplier using a Multi-precision CSA can solve both problems simultaneously by combining a CSA and a CPA. This paper presents an improved MP-CSA which reduces hardware resources and operation time by changing a MP-CSA's carry chain structure. Consequently, the proposed multiplier is more suitable for the module of long bit multiplication and exponentiation using a modular multiplier repeatedly.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.104-112
• /
• 2007

We developed a $7{\times}7$ parallel multiplier using LTPS-TFT. The proposed multiplier has multi-valued logic 7-3 Compressor with folding, 3-2 Compressor, and final carry propagation adder. Architecture minimized the carry propagation. And power consumption reduced by switching the current source to the circuit which is operated in current mode. The proposed multiplier improved PDP by 23%, EDP by 59%, and propagation delay time by 47% compared with Wallace Tree multiplier.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.5
• /
• pp.2680-2700
• /
• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.