• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.3
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• pp.141-145
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• 2006

The line current problem(2-dimensional space : point source) is not easy to analyze the magnetic field using the standard finite element method(FEM), such as overhead trolley line or transmission line. To supplement such a defect this paper is proposed the coupling scheme of analytical solution and FEM. In analysis of the magnetic field using the standard FEM. If the current region is a relatively small compared to the whole region. Therefore the current region must be finely divided using a large number of elements. And the large number of elements increase the number of unknown variables and the use of computer memories. In this paper, an analytical solution is suggested to supplement this weak points. When source is line current and the part of interest is far from line current, the analytical solution can be coupling with FEM at the boundary. Analytical solution can be described by the multiplication of two functions. One is power function of radius, the other is a trigonometric function of angle in the cylindrical coordinate system. There are integral constants of two types which can be established by fourier series expansion. Also fourier series is represented as the factor to apply the continuity of the magnetic vector potential and magnetic field intensity with tangential component at the boundary. To verify the proposed algorithm, we chose simplified model existing magnetic material in FE region. The results are compared with standard FE solution. And it is good agreed by increasing harmonic order.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.727-738
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• 2015

Until recently, power analysis is one of the most popular research issues among various side channel analyses. Since Differential Power Analysis had been first proposed by Kocher et al., various practical power analyses correspond with software/hardware cryptographic devices have been proposed. In this paper, we analyze vulnerability of countermeasure against power analysis exploiting single power trace of public cryptographic algorithm. In ICICS 2010, Clavier et al. proposed Horizontal Correlation Analysis which can recover secret information from a single exponentiation trace and corresponding countermeasures. "Blind operands in LIM", one of their countermeasures, exploits additive blinding in order to prevent leakage of intermediate value related to secret information. However, this countermeasure has vulnerability of having power leakage that is dependant with the message known by an adversary. In this paper, we analyzed vulnerabilities by three attack scenarios and proved them by practical correlation power analysis experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.87-92
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• 2006

An $AB^2$ modular operation is an efficient basic operation for the public key cryptosystems and various systolic architectures for $AB^2$ modular operation have been proposed. However, these architectures have a shortcoming for cryptographic applications due to their high area complexity. Accordingly, this paper presents an partitioned $AB^2$ systolic modular multiplier over GF($2^m$). A dependency graph from the MSB $AB^2$ modular multiplication algorithm is partitioned into 1/3 to get an partitioned $AB^2$ systolic multiplier. The multiplier reduces the area complexity about 2/3 compared with the previous multiplier. The multiplier could be used as a basic building block to implement the modular exponentiation for the public key cryptosystems based on smartcard which has a restricted hardware requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.36-42
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• 2009

This paper proposes the high-performance pipeline architecture for modified Booth multipliers. The proposed multiplier circuits are based on modified Booth algorithm and pipeline architecture which are the most widely used techniques to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The experimental results show that the speed improvement gain exceeds the area penalty and this trend is manifested as the number of pipeline stages increases. It is also important to insert the pipeline registers at the proper positions. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since they operate at GHz ranges, they can be used in the application systems requiring extremely high performance such as optical communication systems.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.3
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• pp.113-123
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• 2007

This paper presents a high-performance elliptic curve cryptographic processor over $GF(2^m)$. The proposed design adopts Lopez-Dahab Montgomery algorithm for elliptic curve point multiplication and uses Gaussian normal basis for $GF(2^m)$ field arithmetic operations. We select m=163 which is the smallest value among five recommended $GF(2^m)$ field sizes by NIST and it is Gaussian normal basis of type 4. The proposed elliptic curve cryptographic processor consists of host interface, data memory, instruction memory, and control. We implement the proposed design using Xilinx XCV2000E FPGA device. Based on the FPGA implementation results, we can see that our design is 2.6 times faster and requires significantly less hardware resources compared with the previously proposed best hardware implementation.

• Journal of Broadcast Engineering
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• v.4 no.2
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• pp.144-154
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• 1999

The binomial sequences are family of orthogonal sequences that can be generated with remarkable simplicity-no multiplications are necessary. This paper introduces a class of non-recursive multidimensional filters for frequency-selective image processing without multiplication operations. The magnitude responses are narrow-band. approximately gaussian-shaped with center frequencies which can be positioned to yield low-pass. band-pass. or high-pass filtering. Algorithms for the efficient implementation of these filters in software or in hardware are described. Also. we show that the binomial QMFs are the maximally flat magnitude square Perfect Reconstruction paraunitary filters with good compression capability and these are shown to be wavelet filters as well. In wavelet transform the original image is decomposed at different scales using a pyramidal algorithm architecture. The decomposition is along the vertical and horizontal direction and maintains constant the number of pixels required to describe the images. An efficient perfect reconstruction binomial QMF-Wavelet signal decomposition structure is proposed. The technique provides a set of filter solutions with very good amplitude responses and band split. The proposed binomial QMF-filter structure is efficient, simple to implement on VLSl. and suitable for multi-resolution signal decomposition and coding applications.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Journal of Digital Contents Society
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• v.16 no.5
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• pp.805-813
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• 2015

Many researchers expect the compressive sensing and sparse recovery problem can overcome the limitation of conventional digital techniques. However, these new approaches require to solve the l1 norm optimization problems when it comes to signal reconstruction. In the signal reconstruction process, the transform computation by multiplication of a random matrix and a vector consumes considerable computing power. To address this issue, parallel processing is applied to the optimization problems. In particular, due to huge size of original signal, it is hard to store the random matrix directly in memory, which makes one need to design a procedural approach in handling the random matrix. This paper presents a new parallel algorithm to calculate random partial Haar wavelet transform based on Single Instruction Multiple Threads (SIMT) platform.

• Journal of the Korean Institute of Intelligent Systems
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• v.7 no.5
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• pp.34-45
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• 1997

In this paper, we present hardware implemcntation of self-organizing feature map (SOFM) neural networkwith constant adaptation gain and binary reinforcement function on FPGA. Whereas a tnme-varyingadaptation gain is used in the conventional SOFM, the proposed SOFM has a time-invariant adaptationgain and adds a binary reinforcement function in order to compensate for the lowered abilityof SOFM due to the constant adaptation gain. Since the proposed algorithm has no multiplication operation.it is much easier to implement than the original SOFM. Since a unit neuron is composed of 1adde $r_tracter and 2 adders, its structure is simple, and thus the number of neurons fabricated onFPGA is expected to he large. In addition, a few control signal: ;:rp sufficient for controlling !he neurons.Experimental results show that each componeni ot thi inipiemented neural network operates correctlyand the whole system also works well.stem also works well.