• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1243-1251
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• 2009

This paper presents design and test results of X-Band Transmit/Receive(T/R) module for active phased-array radar. Active phased array radars typically require solid state T/R modules with high output power, low noise figure, high Third Order Intercept(TOI), and sufficient gain in both transmit and receive. The output power of the module is 9 watts over a wide bandwidth. The noise figure is as low as 2.8 dB. Phase and amplitude are controlled by the 6-bit phase shifter and 5-bit attenuator, respectively. Highly integrated T/R module is achieved by using LTCC(Low Temperature Co-fired Ceramic) multiple layer substrate. The module incorporates a compact digital interface, requires only three supply voltages.