• 전력전자학회논문지
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• 제9권6호
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• pp.620-627
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• 2004

H-브릿지 멀티레벨 인버터는 여러 개의 단상 Power Cell을 직렬로 연결함으로써 저전압 전력용 반도체를 사용하여 고전압을 얻을 수 있고, 정현파에 가까운 출력전압 파형을 얻을 수 있는 멀티레벨 인버터 토폴로지이다. 본 논문은 산업현장에서 신뢰성을 인정받아 많이 사용되고 있는 직렬통신 방식의 일종인 CAN통신 인터럽터를 이용한 H-브릿지 멀티레벨 인버터 Power Cell의 PU 동기화 및 위상전이 방법에 관한 것이다. 제안된 방법의 주요 장점은 주제어기와 셀 제어기 사이에 직렬통신(CAN)을 사용함으로써 주제어기와 셀 제어기의 신호선의 단순화, 주제어기의 부담 감소, Power Cell의 모듈화, 셀 단위의 보호동작 용이, 확장성 향상 그리고 제어 신호 및 Power Cell의 신뢰성을 향상에 있다. 13레벨로 구성된 H-브릿지 멀티레벨 인버터 시험을 통해 제안된 방법의 타당성과 신뢰성을 입증하였다.

• Journal of Electrical Engineering and Technology
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• 제10권6호
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• pp.2277-2287
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• 2015

In recent times, multilevel inverters are given high priority in many large industrial drive applications. However, the reliability of multilevel inverters are mainly affected by the failure of power electronic switches. In this paper, open-switch and short-switch failure of multilevel inverters and its identification using a high performance diagnostic system is discussed. Experimental and simulation studies were carried out on five level cascaded H-Bridge multilevel inverter and its output voltage waveforms were analyzed at different switch fault cases and at different modulation index values. Salient frequency domain features of the output voltage signal were extracted using the discrete wavelet transform multi resolution signal decomposition technique. Real time application of the proposed fault diagnostic system was implemented through the LabVIEW software. Artificial neural network was trained offline using the Matlab software and the resultant network parameters were transferred to LabVIEW real time system. In the proposed system, it is possible to precisely identify the individual faulty switch (may be due to open-switch (or) short-switch failure) of multilevel inverters.

• Journal of Power Electronics
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• 제10권3호
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• pp.262-269
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• 2010

This paper proposes a practical design for a Cascaded H-Bridge Multilevel (CHBM) inverter based on Power Electronics Building Blocks (PEBB) and high performance control to improve current control and increase fault tolerance. It is shown that the expansion and modularization characteristics of the CHBM inverter are improved since the individual inverter modules operate more independently, when using the PEBB concept. It is also shown that the performance of current control can be improved with voltage delay compensation and the fault tolerance can be increased by using unbalance three-phase control. The proposed design and control methods are described in detail and the validity of the proposed system is verified experimentally in various industrial fields.

• 전력전자학회논문지
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• 제15권5호
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• pp.376-380
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• 2010

본 논문에서는 양방향 스위치를 가지는 기존의 5-레벨 인버터를 직렬 결합하여 다수의 출력 전압 레벨을 형성할 수 있는 멀티레벨 인버터 구조를 제안한다. 무엇보다도 제안된 회로의 입력 전압원 크기를 5의 배수로 구성함으로서 보다 많은 수의 레벨을 생성시킬 수 있다. 동일한 수의 출력 전압 레벨 형성시 기존의 Cascaded H-bridge cell 방식보다 스위칭 소자를 줄일 수 있어 시스템 크기, 비용, 전력 손실을 저감시킬 수 있는 장점을 가진다. 두 대의 5-레벨 인버터를 직렬 결합함으로써 25-레벨의 출력전압을 생성시킬 수 있는 인버터에 대한 특성을 분석하고 시뮬레이션과 실험을 통해 타당성을 검증한다.

• Journal of Power Electronics
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• 제13권1호
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• pp.59-69
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• 2013

An alternative technique to control multilevel inverters with vector approximations has been presented. The innovative control method utilizes specially designed two-dimensional hysteresis comparators to simplify the implementation and improve the resultant waveform. The multistage inverter designed with maximum number of levels is operated in such a way to approximate the reference voltage vector by exploiting the large number of multilevel inverter vectors. A three-stage inverter with the main high voltage stage made of three phase, six-switch and singly-fed inverter is considered for application to the proposed design. The proposed control concept is to maintain a higher voltage stage state as long as it can lead to a target vector. High and medium voltage stages controllers are based on surface hysteresis comparators to hold the switching state or to perform the necessary change to achieve its reference voltage with minimal switching losses. The low voltage stage controller is designed to approximate the target reference voltage to the nearest inverter vector using the nearest integer rounding and adjustment comparators. Model simulation and prototype test results show that the proposed control technique clearly outperforms the previous control methods.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권12호
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• pp.691-700
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• 1999

This paper proposes a novel switching strategy of 1Mvar STATCON using cascade multilevel H-bridge inverter(HBI) for FACTS application. To control the reactive power instantaneously, the d-q dynamic system model is described and analyzed. A single pulse pattern based on the SHEM(Selective Harmonic Elimination Method) technique is determined from the look-up table to reduce the line current harmonics and a rotating fundamental frequency switching scheme is presented to adjust the DC voltage of each inverter capacitor at the same value. So the voltage unbalance problem between separately DC bus voltage is improved by using the proposed switching scheme. As a result, the presented inverter configuration not only reduces the system complexity by eliminating the isolation at the AC input side transformer but also improves the dynamic response to the step change of reactive power.

• 전기학회논문지
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• 제56권5호
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• pp.892-897
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• 2007

This paper presents the output filter design and the output characteristic analysis by cut-off frequency set up of the LCR filter on NPC multi-level inverter with trap-filter. The single-phase NPC three-level inverter operates at low switching frequency. The proposed LC trap filter is comprised of a conventional LCR output filter, by using LC trap filter the need for high damping resistor and low LC cut-off frequency is eliminated. Also. low damping resistor is increased the output filter system. The multilevel inverter system used NPC type inverter in proper system for high power application and controller is used DSP(TMS320C31). The effectiveness of proposed system confirmed the validity through SPICE simulation and experimental results.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권9호
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• pp.598-606
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• 2000

This paper proposes a new snubber circuit for 4-level inverter and converter. The snubber circuit makes use of Undeland snubber and McMurray efficient snubber as basic snubber unit and can be regarded as a generalized combined Undeland and McMurray efficient snubber. The proposed snubber keeps such good features as fewer number of components improved efficiency due to low snubber loss capability of clamping overvoltage across main switching devices and no unbalance problem of blocking voltage. Furthermore the proposed concept of constructing a snubber circuit for 4-level inverter and converter can apply to any level of converterand inverter.

• Journal of international Conference on Electrical Machines and Systems
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• 제1권4호
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• pp.448-456
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• 2012

This paper presents a multilevel inverter configuration which is designed by insertion of a bidirectional switch between capacitive voltage sources and a conventional H-bridge module. The modified inverter can produce a better sinusoidal waveform by increasing the number of output voltage levels. By serial connection of two modified H-bridge modules, it is possible to produce 9 output voltage levels including zero. There are 24 basic switching patterns with the 9 output voltage levels. Among the patterns, we select the 2 most efficient switching patterns to get a lower switching loss and minimum dv/dt stress. We then analyze characteristics of Total Harmonic Distortion (THD) of the output voltage with variation of input voltage by computer-aided simulations and experiments.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.225-227
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• 2008

This paper deals with the implementation on a Field Programmable Gate Array (FPGA) of PWM switching patterns for a voltage multilevel inverter. The reference data in main microcontroller is transmitted to the FPGA through 16 general purpose I/O ports. Herein, three-phase reference voltage signals are addressed by the last 2-bit (bit 15-14) and their data are assigned in remaining 14-bit, respectively. The carrier signals are created by 16-bit counter in up-down counting mode inside FPGA according to desirable topology. Each reference signal is compared with all carrier signals to generate corresponding PWM switching patterns for control of the multilevel inverter. Useful advantages of this scheme are easy implementation, simple software control and flexibility in adaptation to produce many PWM signals. Some simulations and experiments are carried out to validate the proposed method.