• Journal of Power Electronics
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• v.10 no.3
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• pp.277-284
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• 2010

This paper presents a novel hybrid carrier based space vector modulation for cascaded multilevel inverters. The proposed technique inherits the properties of carrier based space vector modulation and the fundamental frequency modulation strategy. The main characteristic of this modulation are the reduction of power loss, and improved harmonic performance. The carrier based space vector modulation algorithm is implemented with a TMS320F2407 digital signal processor. A Xilinx Complex Programmable Logic Device is used to develop the hybrid PWM control algorithm and it is integrated with a digital signal processor for hybrid carrier based space vector PWM generation. The inverter offers less weighted total harmonic distortion and it operates with equal electrostatic and electromagnetic stress among the power devices. The feasibility of the proposed technique is verified by spectral analysis, simulation, and experimental results.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.541-546
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• 1998

This paper proposes a new snubber circuit for multilevel inverter and converter. The snubber circuit makes use of Undeland snubber as basic snubber unit and can be regraded as a generalized Undeland snubber. The proposed snubber keeps such good features as fewer number of components, improved efficiency due to low loss snubber, capability of clamping overvoltage across main switching devices, and no unbalance problem of blocking voltage. Furthermore, the proposed concept of constructing a snubber circuit for multilevel inverter and converter can apply to any kind of basic snubber unit such as Holtz nondissipative snubber, McMurray efficient snubber, Lauritzen lossless snubber, etc which have been utilized for two-level inveter.

• Journal of Power Electronics
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• v.11 no.1
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• pp.21-27
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• 2011

In this paper, an approach to reduce common-mode voltage (CMV) at the output of multilevel inverters using a phase opposition disposed (POD) sinusoidal pulse width modulation (SPWM) technique is proposed. The SPWM technique does not require computations therefore, this technique is easy to implement on-line in digital controllers. A good tradeoff between the quality of the output voltage and the magnitude of the CMV is achieved in this paper. This paper realizes the implementation of a POD-SPWM technique to reduce CMV using a five-level diode clamped inverter for a three phase induction motor. Experimental and simulation results demonstrate the feasibility of the proposed technique.

• Journal of information and communication convergence engineering
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• v.1 no.3
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• pp.163-168
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• 2003

This paper presents a cascade multilevel PWM rectifier without the isolation transformers for energy build-up at each inverter modules. The features and advantages of the proposed PWM rectifier can be summarized as follows; I) It realizes the high power high voltage AC/DC power conversion, 2) It uses no transformer which is bulky and heavy, 3) It has hybrid structure so that switching devices can be effectively utilized, 4) It produces high quality AC current even in high power high voltage applications, 5) The input power factor remains unity by simple modulation index control. The multilevel rectifier is analyzed by using the circuit DQ transformation whereby the characteristics and control equations are obtained. Finally, it will be shown that the system simulation reveals the validity of analyses.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2168-2180
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• 2014

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

• Journal of Magnetics
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• v.21 no.1
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• pp.83-93
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• 2016

Due to their performances and inherent benefits, especially in medium-voltage and high-power applications, multilevel inverters have received an increasing attention in real world industrial applications. The present paper deals with a review of the main multilevel inverter topologies as well their most common derived and hybrid structures quoted in previous research works. It also encompasses an investigation on voltage harmonic elimination and THD estimation. For that reason, the paper summarizes the most relevant modulation techniques used so far to enhance the output voltage quality. Theoretical formulas evoked in the literature, for calculating the output voltage THD upper and lower bounds are reported and verified by adequate simulations.

• Journal of Power Electronics
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• v.15 no.1
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• pp.96-105
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• 2015

In recent years, the multilevel converters have been given more attention due to their modularity, reliability, failure management and multi stepped output waveform with less total harmonic distortion. This paper presents a novel symmetric multilevel inverter topology with reduced switching components to generate a high quality stepped sinusoidal voltage waveform. The series and parallel combinations of switches in the proposed topology reduce the total number of conducting switches in each level of output voltages. In addition, a comparison between the proposed topology with another topology from the literature is presented. To verify the proposed topology, the computer based simulation model is developed using MATLAB/Simulink and experimentally with a prototype model results are then compared.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.593-597
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• 2003

Multilevel power conversion technology has received increasing attention recently for high power applications. The converters with the technology are suitable for high voltage and high power applications due to their ability to synthesize waveforms with better harmonic spectrum and apply for the high voltage equipment with a limited voltage rating of device. In the family of multilevel inverters, the topologies based on cascaded H-bridges are particularly attractive because of their modularity and simplicity of control. This paper presents multilevel inverter with cascaded H-bridge for large-power motor drives. The main features of this drive 1) reduce harmonic injection 2) can generate near-sinusoidal voltages, 3) have almost no common-mode voltage; 4) are low dv/dt at output voltage; 5)do not generate significant over-voltage on motor terminal; The topology of the developed product is presented and the feasibility study of the inverter on 3300v 1MVA 7-level H-bridge type was tarried out with experiments.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2272-2283
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• 2016

This paper proposes a power conditioning system (PCS) for distributed photovoltaic (PV) applications using an asymmetric cascaded multilevel inverter with a single PV source. One of the main disadvantages of the cascaded multilevel inverters in PV systems is the requirement of multiple isolated DC sources. Using multiple PV strings leads to a compromise in either the voltage balance of individual H-bridge cells or the maximum power point tracking (MPPT) operation due to localized variations in atmospheric conditions. The proposed PCS uses a single PV source with a flyback DC-DC converter to facilitate a reduction of the required DC sources and to maintain the voltage balance during MPPT operation. The flyback converter is used to provide input for low-voltage H-bridge cells which processes only 20% of the total power. This helps to minimize the losses occurring in the proposed PCS. Furthermore, transient analyses and controller design for the proposed PCS in both the stand-alone mode and the grid-connection mode are presented. The feasibility of the proposed PCS and its control scheme have been tested using a 1kW hardware prototype and the obtained results are presented.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2139-2149
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• 2016

In this study, a new type of cascaded modular multilevel inverters (CMMLIs) is presented which is able to produce a considerable number of output voltage levels with a reasonable number of components. Accordingly, each series stage of the proposed CMMLI is comprised of two same basic units that are connected with each other through two unidirectional power switches without aiming any of the full H-bridge cells. In addition, since the potentiality for generating a higher number of output voltage levels in CMMLIs hinges on the magnitude of the dc voltage sources used in each series unit, in the rest of this paper, four different algorithms for determining an appropriate value for the dc sources' magnitude are also presented. In the following, a comprehensive topological analysis between some CMMLI structures reported in the literature and proposed structure along with several simulation and experimental results will be also given to validate the lucrative benefits and viability of the proposed topology.