• ETRI Journal
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• v.20 no.4
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• pp.327-345
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• 1998

This paper deals with the problem of one-to-one mapping of 2$^n$ task modules of a parallel program to an n-dimensional hypercube multicomputer so as to minimize the total communication cost during the execution of the task. The problem of finding an optimal mapping has been proven to be NP-complete. First we show that the mapping problem in a hypercube multicomputer can be transformed into the problem of finding a set of maximum cutsets on a given task graph using a graph modification technique. Then we propose a repeated mapping scheme, using an existing graph bipartitioning algorithm, for the effective mapping of task modules onto the processors of a hypercube multicomputer. The repeated mapping scheme is shown to be highly effective on a number of test task graphs; it increasingly outperforms the greedy and recursive mapping algorithms as the number of processors increases. Our repeated mapping scheme is shown to be very effective for regular graphs, such as hypercube-isomorphic or 'almost' isomorphic graphs and meshes; it finds optimal mappings on almost all the regular task graphs considered.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.120-128
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• 1993

In this paper, an implementation of high-speed parallel processing system for neural network design on the multicomputer network is presented. Linear speedup expandability is increased by reducing the synchronization penalty and the communication overhead. Also, we presented the parallel processing models and their performance evaluation models for each of the parallization methods of the neural network. The results of the experiments for the character recognition of the neural network bases on the proposed system show that the proposed approach has the higher linear speedup expandability than the other systems. The proposed parallel processing models and the performance evaluation models could be used effectively for the design and the performance estimation of the neural network on the multicomputer network.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.610-617
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• 1987

This thesis is concerned with fault-tolerance of a B-net (Beta-network) which is a kind of interconnection network in the multicomputer system. In this paper, a method for obtaining Maximal Tolerable Fault Set(MTFS) of link line connecting switching elements in the arbitrary B-net is presented. Using this method, it is seen that testing of DFA capability is possible when s-a-faults of link line occur, and criterion for determining degree of fault- tolerance of a B-net in terms of link line is introduced.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.197-208
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• 1996

A neural network-based PSRI(position, scale, and rotation invariant) feature extraction and ATR (automatic target recognition) system are proposed and an efficient parallel implementatio of the proposed system using multicomputer is also presented. In the proposed system, the scale and rotationinvariant features are extracted from the contour projection of the number of edge pixels on each of the concentric circles, which is input t the cooperative network. We proposed how to decide the optimum depth and the width of the parallel pipeline system for real time applications by modeling the proposed system into a parallel pipeline implementation method using transputers is also proposed. The implementation results show that we can extract PSRI features less sensitive to input variations, and the speedup of the proposed ATR system is about 7.55 for the various rotated and scaled targets using 8-node transputer system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.10
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• pp.90-97
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• 1996

This paper presents an efficient parallel implementation and its performance evaluations of a SOFM neural netowrk on the multicomputer. We investigate the parallel performance as the size of a neural network N, the number of the patterns L, and the number of the processors p increase. We propose an analytica performance evaluation model for eac of the parallel implementations and verified the validity of the model through experiments. Analytical result show that the number of processors for a maximum speedup of the network decomposition nd the training-set decomposition increases in proportion to .root.N and .root.L, respectively. The performances of the both decompositions depend on the number of training patterns L and the size of the neural network N and, if L.geq.0.423N, the performance of trhe training-set decomposition is proved to be better than that of the network decomposition.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.12
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• pp.75-82
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• 1991

We proposed an optimal parallel implementation of an optimization neural network with linear increase of speedup by using multicomputer system and presented performance analysis model of the system. We extracted the temporal-and the spatial-parallelism from the optimization neural network and constructed a parallel pipeline processing model using the parallelism in order to achieve the maximum speedup and efficiency on the CSP architecture. The results of the experiments for the TSP using the Transputer system, show that the proposed system gives linear increase of speedup proportional to the size of the optimization neural network for more than 140 neurons, and we can have more than 98% of effeciency upto 16-node system.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2823-2834
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• 1998

This paper deals with the problem of one-to-one mapping of $2^n$ task modules of a parallel program to an n-dimensional hypercube multicomputer so as to minimize to total communication cost during the execution of the task. The problem of finding an optimal mapping has been proven to be NP-complete. We first propose a graph modification technique which transfers the mapping problem in a hypercube multicomputer into the problem of finding a set of maximum cutsets on a given task graph. Using the graph modification technique, we then propose a repeated mapping scheme which efficiently finds a one-to-one mapping of task modules to a hypercube multicomputer by repeatedly applying an existing bipartitioning algorithm on the modified graph. The repeated mapping scheme is shown to be highly effective on a number of test task graphs, it increasingly outperforms the greedy and recursive mapping algorithms as the number of processors increase. The proposed algorithm is shown to be very effective for regular graph, such as hypercube-isomorphic or 'almost' isomorphic graphs and meshes; it finds optimal mapping on almost all the regular task graphs considered.

• The KIPS Transactions:PartA
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• v.8A no.3
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• pp.245-252
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• 2001

Multicomputer systems achieve high performance by utilizing a number of computing nodes. Multidimensional meshes have become popular as multicomputer architectures due to their simplicity and efficiency. In this paper we propose an efficient processor allocation scheme for 3D torus based on first-fit approach. The scheme minimizes the allocation time by effectively manipulating the 3D information an 2D information using CST (Coverage Status Table). Comprehensive computer simulation reveals that the allocation time of the proposed scheme is always smaller than the earlier scheme based on best-fit approach, while allowing comparable processor utilization. The difference gets more significant as the input load increases. To investigate the performance of the proposed scheme with different scheduling environment, non-FCFs scheduling policy along with the typical FCFS policy is also studied.

• Proceedings of the Korea Society for Simulation Conference
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• 1994.10a
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• pp.32-32
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• 1994

In this example, a message passing based multicomputer system with general interdonnedtion network is considered. After multicomputer systems are developed with morm-hole routing network, topologies of interconecting network are not major considertion for process management and resource sharing. Tehre is an independeent operating system kernel oneach node. It communicates with other kernels using message passingmechanism. Based on this architecture, the problem is how mech does performance degradation will occur in the case of processor sharing on multicomputer systems. Processor sharing between application programs is veryimprotant decision on system performance. In almost cases, application programs running on massively parallel computer systems are not so much user-interactive. Thus, the main performance index is system throughput. Each application program has various communication patterns. and the sharing of processors causes serious performance degradation in hte worst case such that one processor is shared by two processes and another processes are waiting the messages from those processes. As a result, considering this problem is improtant since it gives the reason whether the system allows processor sharingor not. Input data has many parameters in this simulation . It contains the number of threads per task , communication patterns between threads, data generation and also defects in random inupt data. Many parallel aplication programs has its specific communication patterns, and there are computation and communication phases. Therefore, this phase informatin cannot be obtained random input data. If we get trace data from some real applications. we can simulate the problem more realistic . On the other hand, simualtion results will be waseteful unless sufficient trace data with varisous communication patterns is gathered. In this project , random input data are used for simulation . Only controllable data are the number of threads of each task and mapping strategy. First, each task runs independently. After that , each task shres one and more processors with other tasks. As more processors are shared , there will be performance degradation . Form this degradation rate , we can know the overhead of processor sharing . Process scheduling policy can affects the results of simulation . For process scheduling, priority queue and FIFO queue are implemented to support round-robin scheduling and priority scheduling.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.612-614
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• 2000

하이퍼큐브의 성능을 좌우하는 중요한 요소 중 하나가 프로세서간의 통신이다. 그리고 병렬 컴퓨터에서 프로세서의 수가 증가함에 따라, 구성요소들이 오류가 날 확률도 높아졌다. 이러한 이유로, 오류 난 구성요소들이 있어도 다중 전송이 가능하게 효율적으로 설계하는 것이 중요하다. 본 논문에서는 최근에 제안된 완전 도달성 정보와 새로 추가한 국지적 정보를 이용해서 라우팅 알고리즘을 제안하고, 이것을 바탕으로 다중 전송 성공률이 높은 새로운 다중 전송 알고리즘을 제안하였다. 시뮬레이션을 통하여 제안한 기법은 기존의 기법 보다 통신량의 차이는 거의 없으면서, 다중 전송 성공률이 목적지 노드 수에 따라 5~15% 가량 향상시킬 수 있었다.