• Journal of the Korean Institute of Plant Engineering
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• v.23 no.4
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• pp.29-38
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• 2018

Through process quality information, the time required for process quality analysis has been drastically shortened, the process defect rate has been reduced, and the manufacturing lead time has been shortened and the on-time delivery rate has been improved. Therefore, The purpose of this study is to develop a quality information analysis system model that effectively shortens the time required for process quality analysis in automobile safety belt parts manufacturing process. As a result of experiments on communication operation between manufacturing execution system (MES) quality server, injection machine control computer, injection machine programmable logic controller (PLC) and terminal, in analyzing quality information, the conventional handwriting input method took an average of 20 minutes, but the new multi-network method took about 2 minutes on average. In addition, the process defect rate was reduced by 13% and the manufacturing lead time was shortened from 28 hours to 20 hours. The delivery compliance rate improved from 96 to 99%.

• The Journal of Engineering Research
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• v.6 no.1
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• pp.111-124
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• 2004

The advanced semiconductor technology and electronic design automation(EDA) tools make it possible to implement the system on the programmable logic devices. The electronic design method is also changing from schematic capture to hardware description language. In this paper, I present the architecture of multi-dimensional digital filter which can be efficiently implemented on PLDs. This is based on the former research results which are called algorithm decomposition technique. Algorithm decomposition technique is used to obtain the computational primitive from the state space equations of the multi-dimensional digital filtering algorithm. The obtained computational primitive is designed with VHDL. This can be used to implement the filtering system as a component. The designed filtering system is implemented on the PLD. Therefore, the filter can be upgradable on system. It is greatly reduced the time-to-market time of the system that is based on the multi-dimensional filter.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.925-928
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• 1999

A multi-channel gas leakage monitoring system was designed and fabricated by using CPLD(complex Programmable Logic .Device) for monitoring and controlling the leakage of natural gas from supplying-pipes under the ground. Fabricated SnO$_2$thick film gas sensor elements were attached on safeguard steel plate of natural gas supplying pipes, and the local monitoring system in this study received the signal from the gas sensors. The monitoring system was implemented by using CPLD chip to reduce the development time and implement simple one chip system. The time division multi-channel system received the input signal from individual gas sensor at one of divided times by multiplexor and signal processed sequentially. The system reduced the size of peripheral circuit resulted in implementation of creditable simple system.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• International Journal of Contents
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• v.11 no.4
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• pp.70-76
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• 2015

The development of technology provides and increases security as well as convenience for humans. The development of new technology directly affects the standard of life thanks to smart home automatic control systems. This paper describes a door control, automatic curtain, home security (CCTV, fire, gas, safe, etc.), home control (energy, light, ventilation, etc.) and web-based smart home automatic controller. It also describes the use of ARM (Advanced RISC Machines) for automatic control of home equipment, a Multi-Axes Servo Controller using FPGA (Field Programmable Gate Array) and PLC (programmable logic controller). Additionally, it describes the development of a HTML editor using web auto control software. The tab loading time (7 seconds) is faster when using ARM-based web browser software instead of Chrome and Firefox is used because the browser has a small memory footprint (300M). This system is realized by web auto controller language which controls and uses PLCs that are easier than existing devices. This smart home automatic control technology can control smart home equipment anywhere and anytime and provides a remote interface through mobile equipment.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.2
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• pp.151-159
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• 2022

In this paper, we implement a digital multi-beamformer using FPGA(Field Programmable Gate Array) which has advantages in parallel and real-time data processing. This is accomplished through the use of not only high-speed data communication but also multiple beam forming, which is currently required by MFR(Multi Function Radar). As a result, the beamformer can process 24 Gbps throughput in real-time and form 5 digital beams at the same time. It is also compared to the results of Matlab simulations. We demonstrate how an implemented beamformer can be used in an MFR system by using a digital array antenna.

• Journal of Positioning, Navigation, and Timing
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• v.13 no.2
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• pp.149-158
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• 2024

Global Navigation Satellite System (GNSS) receivers are becoming increasingly sophisticated, equipped with advanced features and precise specifications, thus demanding efficient and high-performance hardware platforms. This paper presents the design and implementation of a Field-Programmable Gate Array (FPGA)-based GNSS receiver development platform for multi-band signal processing. This platform utilizes a FPGA to provide a flexible and re-configurable hardware environment, enabling real-time signal processing, position determination, and handling of large-scale data. Integrated signal processing of L/S bands enhances the performance and functionality of GNSS receivers. Key components such as the RF frontend, signal processing modules, and power management are designed to ensure optimal signal reception and processing, supporting multiple GNSS. The developed hardware platform enables real-time signal processing and position determination, supporting multiple GNSS systems, thereby contributing to the advancement of GNSS development and research.

• Journal of Information Processing Systems
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• v.5 no.2
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• pp.105-116
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• 2009

To solve the general problems surrounding the application of genetic algorithms in stereo matching, two measures are proposed. Firstly, the strategy of simplified population-based incremental learning (PBIL) is adopted to reduce the problems with memory consumption and search inefficiency, and a scheme for controlling the distance of neighbors for disparity smoothness is inserted to obtain a wide-area consistency of disparities. In addition, an alternative version of the proposed algorithm, without the use of a probability vector, is also presented for simpler set-ups. Secondly, programmable graphics-hardware (GPU) consists of multiple multi-processors and has a powerful parallelism which can perform operations in parallel at low cost. Therefore, in order to decrease the running time further, a model of the proposed algorithm, which can be run on programmable graphics-hardware (GPU), is presented for the first time. The algorithms are implemented on the CPU as well as on the GPU and are evaluated by experiments. The experimental results show that the proposed algorithm offers better performance than traditional BMA methods with a deliberate relaxation and its modified version in terms of both running speed and stability. The comparison of computation times for the algorithm both on the GPU and the CPU shows that the former has more speed-up than the latter, the bigger the image size is.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.212-215
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• 2005

The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.11
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• pp.949-958
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• 2016

This paper presents the new development result of the multi-band, the multi-mode SDR(Software Defined Radar) platform. The SDR hardware platform is implemented by using the reconfigurable multi-band RF transceiver and antenna modules of S, X, and K-bands, and a programmable signal processing module. The SDR software platform is implemented by using the multi-mode waveform generation of CW, Pulse, FMCW, and LFM Chirp as well as the adaptable algorithm library of signal processing and open API software modules. Through the integrated test of the SDR platform, the operational performance was verified in real-time. Also, through the field-application test, the ground target and air-vehicle drone target were successfully detected and their test results were presented.