• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.172-172
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• 2009

$BaTiO_3$는 perovskite 구조를 가지는 대표적인 강유전체 재료로서 MLCC(Multi Layer Ceramic Capacitor), PTC thermistor등에 널리 사용되어지고 있다. 최근 고용량 MLCC 의 상업화와 함께 나노크기를 갖는 tetragonal phase의 $BaTiO_3$ 입자를 합성하기 위한 다양한 제조방법이 제시되고 있다. 또한 유전 특성과 온도특성 및 신뢰성을 향상시키기 위해 많은 첨가제들이 연구되어지고 있다. 따라서 이 번 연구에서는 선행 연구를 통해 얻어진 high energy mill을 이용한 고상반응법으로 제조된 $BaTiO_3$를 사용하였으며, 제조된 $BaTiO_3$ 분말에 glass frit를 첨가하여 소결온도 및 유전특성의 변화를 관찰하였다. 제조된 $BaTiO_3$ 분말은 200nm이하의 구형화와 균일한 입자크기를 보였으며, 선행연구를 통해 최적화된 glass frit의 양인 2.53wt%를 첨가하였고 1170, 1200, $1230^{\circ}C$에서 소결하여 소결온도에 따른 변화를 관찰하였다. 실험방법으로는 원료를 혼합하기 위하여 24시간 ball-mill을 이용하여 혼합하였으며, $\Phi15$로 성형하여 소결을 진행하였다. 실험진행 결과 모든 시편에서의 비유전율은 glass frit가 첨가되지 않은 조성보다 높게 나타났으며, $1200^{\circ}C$에서 소결한 시편의 비유전율($\varepsilon_r$)은 2300으로 glass frit가 첨가되지 않은 조성과 비교하여 21% 증가하여 최대치를 나타냈다. 또한 소결온도 $1200^{\circ}C$ 이상에서의 모든 시편에서는 95% 이상의 상대밀도를 나타내어, glass frit가 소결조제로써의 역할을 하는 것으로 나타났다. 따라서 본 연구를 통해 glass frit첨가로 인한 소결온도 감소 및 유전특성이 증가하는 것을 확인 하였다.

• Korean Journal of Materials Research
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• v.20 no.11
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• pp.600-605
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• 2010

In order to meet the requirements of faster speed and higher packing density for devices in the field of semiconductor manufacturing, the development of Cu/Low k device material is explored for use in multi-layer interconnection. SiOC(-H) thin films containing alkylgroup are considered the most promising among all the other low k candidate materials for Cu interconnection, which materials are intended to replace conventional Al wiring. Their promising character is due to their thermal and mechanical properties, which are superior to those of organic materials such as porous $SiO_2$, SiOF, polyimides, and poly (arylene ether). SiOC(-H) thin films containing alkylgroup are generally prepared by PECVD method using trimethoxysilane as precursor. Nano voids in the film originating from the sterichindrance of alkylgroup lower the dielectric constant of the film. In this study, methyltriphenylsilane containing bulky substitute was prepared and characterized by using NMR, single-crystal X-ray, GC-MS, GPC, FT-IR and TGA analyses. Solid-state NMR is utilized to investigate the insoluble samples and the chemical shift of $^{29}Si$. X-ray single crystal results confirm that methyltriphenylsilane is composed of one Si molecule, three phenyl rings and one methyl molecule. When methyltriphenylsilane decomposes, it produces radicals such as phenyl, diphenyl, phenylsilane, diphenylsilane, triphenylsilane, etc. From the analytical data, methyltriphenylsilane was found to be very efficient as a CVD or PECVD precursor.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1244-1245
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• 2008

Recently, piezoelectric transformer is applied to wide fields. Multi layer piezoelectric transformer has the advantage of high step up ratio, electromechanical coupling coefficient(Kp) and mechanical quality factor(Qm), but is indicated of peeling-phenomenon of electrode, rising sintering temperature made price of costly electrode. So in this study, it discuss on method for fabrication of rosen type piezoelectric transformers. For the fabrication as rosen type piezoelectric transformers, synthesized the powder using 0.01Pb$(ni_{1/3}Nb_{2/3})O_3$ - 0.08Pb$(Mn_{1/3}Nb_{2/3})O_3$ - 0.91Pb$(Zr_{0506}Ti_{0496})O_3$ (abbreviated as PNN-PMN-PZT) ceramics. The density, microstructure, dielectric and piezoelectric properties as a function of sintering temperature were investigated. The results indicated that the optimized properties of ceramics were obtained at sintering temperature of 1200$^{\circ}C$, showed the value of $d_{33}$=273pC/N, $K_p$=0.60 $Q_m$=1585, ${\varepsilon}_r$=1454, density=7.917$g/cm^3$ and $tan{\delta}$=0.0064.

• Ceramist
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• v.21 no.2
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.656-656
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• 2013

Multi-layer ceramic capacitor (MLCC)는 '전자산업의 쌀'이라고 일컬어 질만큼, 전자부품내에서 매우 중요하고 핵심적인 역할을 하며, 그 응용분야 또한 매우 광범위하다. 이러한 MLCC는 그 사용처에 따라, 초고용량 MLCC, 고전압용 MLCC, 저가제품용 MLCC, 그리고 고용량용 MLCC 등등으로 나뉘어진다. 이 중 최근 각광 받고 있는 스마트폰, 태플릿PC 등의 전자제품군에 사용되는 초고용량 MLCC의 경우, 높은 유전상수 값을 지닌 BaTiO3 기반의 물질이 일반적으로 사용되어지고 있으며, 또한 더 높은 용량(capacitance)을 얻기 위하여 해마다 유전체층의 두께가 점점 줄어들고 있고, 이러한 얇은 유전체층을 만들어 내기위해 유전체층의 결정립 크기도 수 마이크로미터에서 수백, 수십 나노미터 사이즈로 점점 작아지고 있는 상황이다. 하지만 점점 줄어들고 있는 유전체층의 두께와 결정립 크기의 추세와는 상관없이, 전기회로에서 요구되는 인가전압은 줄어들지 않고 일정하게 유지되고 있기 때문에, 유전체층의 내전압 특성은 전자제품의 높은 신뢰성을 위해서 날이 갈수록 중요시 되고 있다. 특히, 수백 나노미터 이하의 결정립 크기를 갖는 BaTiO3 유전체층의 내전압 특성은, 다양한 내전압 특성 메커니즘이 연구되어진 수 마이크로미터 대역의 결정립 크기를 갖는 BaTiO3 유전체층과는 다르게, MLCC 제조공정상의 한계와 BaTiO3의 결정립 성장이라는 어려움 때문에, 그 연구가 전무하다 할 수 있다. 따라서 본 연구에서는 수십 나노미터 결정립 크기를 갖는 BaTiO3 막을 만들어낼 수 있는 에어로졸 데포지션 공정을 이용하여 수십 나노미터 결정립 크기를 갖는 BaTiO3 막을 제조 하였으며, 이 막을 다양한 온도 조건에서 후속 열처리를 통한 결정립 성장을 통해 수십에서 수백 나노미터의 다양한 결정립 크기를 갖는 BaTiO3 막의 내전압 특성을 분석하였다.

• Korean Journal of Materials Research
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• v.18 no.3
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• pp.148-152
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• 2008

A new cost-effective atomic layer deposition (ALD) technique, known as Proximity-Scan ALD (PS-ALD) was developed and its benefits were demonstrated by depositing $Al_2O_3$ and $HfO_2$ thin films using TMA and TEMAHf, respectively, as precursors. The system is consisted of two separate injectors for precursors and reactants that are placed near a heated substrate at a proximity of less than 1 cm. The bell-shaped injector chamber separated but close to the substrate forms a local chamber, maintaining higher pressure compared to the rest of chamber. Therefore, a system configuration with a rotating substrate gives the typical sequential deposition process of ALD under a continuous source flow without the need for gas switching. As the pressure required for the deposition is achieved in a small local volume, the need for an expensive metal organic (MO) source is reduced by a factor of approximately 100 concerning the volume ratio of local to total chambers. Under an optimized deposition condition, the deposition rates of $Al_2O_3$ and $HfO_2$ were $1.3\;{\AA}/cycle$ and $0.75\;{\AA}/cycle$, respectively, with dielectric constants of 9.4 and 23. A relatively short cycle time ($5{\sim}10\;sec$) due to the lack of the time-consuming "purging and pumping" process and the capability of multi-wafer processing of the proposed technology offer a very high through-put in addition to a lower cost.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.172-178
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• 2019

This paper has designed, fabricated, and analyzed the passive devices realized using low temperature co-fired ceramic (LTCC) multi layer substrates by dividing into the shrinkage process and the non-shrinkage process. Using two types of ceramic materials with dielectric constant 7 or 40, we have fabricated the same shape of various elements in 2 different processes and compared the characteristics. For the substrate of dielctric constant 40, compared with the shrinkage process which has 17% shrink in the X and Y directions with 36% shrink in the Z direction, the non-shrinkage process has 43% shrink in the Z direction without shrink in the X and Y directions, so high dimensional accuracy and surface flatness can be obtained. The inductances and capacitances of the fabricated elements are estimated from measurement using empirical analysis equations of parameters and implemented as a design library. Depending on the substrate and the process, the inductance and capacitance depending on the turn number of winding and unit area have been measured, and empirical polynomials are proposed to predict element values.

• The Journal of Engineering Geology
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• v.25 no.3
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• pp.349-356
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• 2015

Although geophysical methods are useful and generally provide valuable information about the subsurface, it is important to recognize their limitations. A common limitation is the lack of sufficient contrast in physical properties between different layers. Thus, multiple methods are commonly used to best constrain the physical properties of different layers and interpret each section individually. Ground penetrating radar (GPR) and shallow seismic reflection (SSR) methods, used for shallow and very shallow subsurface imaging, respond to dielectric and velocity contrasts between layers, respectively. In this study, we merged GPR and SSR data from a test site within the Cheongui granitic mass, where the water table is ~3 m deep all year. We interpreted the data in combination with field observations and existing data from drill cores and well logs. GPR and SSR reflections from the tops of the sand layer, water table, and weathered and soft rocks are successfully mapped in a single section, and they correlate well with electrical resistivity data and SPS (suspension PS) well-logging profiles. In addition, subsurface interfaces in the integrated section correlate well with S-wave velocity structures from multi-channel analysis shear wave (MASW) data, a method that was recently developed to enhance lateral resolution on the basis of CMP (common midpoint) cross-correlation (CMPCC) analysis.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.228-238
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• 1992

An investigation on the step-coverage of PECVD and $O_3$ ThCVD oxides was undertaken to implement into the void-free inter metal dielectric planarization using multi-chamber system for the submicron double level metallization. At various initial aspect ratios the instantaneous aspect ratios were measured through modelling and experiment by depositing the oxides up to $0.9{\mu}m$ in thickness in order to monitor the onset of void formation. The modelling was found to be in a good agreement with the observed instantaneous aspect ratio of TEOS-based PECVD oxide whose re-entrant angle was less than $5^{\circ}$. It is demonstrated that either keeping the instantaneous aspect ratio of PECVD oxide as a first layer less than a factor of 0.8 or employing Ar sputter etch to create sloped oxide edge ensures the void-free planarization after$O_3$ ThCVD oxide deposition whose step-coverage is superior to PECVD oxide. It has been observed that $O_3$ ThCVD oxide etchback scheme has shown higher yield of via contact chain than non etchback process, with resistance per via contact of $0.1~0.3{\Omega}/{\mu}m^2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.200-200
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• 2010

In recent times, metal oxide semiconductors thin films transistor (TFT), such as zinc and indium based oxide TFTs, have attracted considerable attention because of their several advantageous electrical and optical properties. There are many deposition methods for fabrication of ZnO-based materials such as chemical vapor deposition, RF/DC sputtering and pulsed laser deposition. However, these vacuum process require expensive equipment and result in high manufacturing costs. Also, the methods is difficult to fabricate various multicomponent oxide semiconductor. Recently, several groups report solution processed metal oxide TFTs for low cost and non vacuum process. In this study, we have newly developed solution-processed TFTs based on Ti-related multi-component transparent oxide, i. e., InTiO as the active layer. We propose new multicomponent oxide, Titanium indium oxide(TiInO), to fabricate the high performance TFT through the sol-gel method. We investigated the influence of relative compositions of Ti on the electrical properties. Indium nitrate hydrate [$In(NO^3).xH_2O$] and Titanium isobutoxide [$C_{16}H_{36}O_4Ti$] were dissolved in acetylacetone. Then monoethanolamine (MEA) and acetic acid ($CH_3COOH$) were added to the solution. The molar concentration of indium was kept as 0.1 mol concentration and the amount of Ti was varied according to weighting percent (0, 5, 10%). The complex solutions become clear and homogeneous after stirring for 24 hours. Heavily boron (p+) doped Si wafer with 100nm thermally grown $SiO_2$ serve as the gate and gate dielectric of the TFT, respectively. TiInO thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films annealed in a tube furnace at $500^{\circ}C$ for 1hour under oxygen ambient. The 5% Ti-doped InO TFT had a field-effect mobility $1.15cm^2/V{\cdot}S$, a threshold voltage of 4.73 V, an on/off current ratio grater than $10^7$, and a subthreshold slop of 0.49 V/dec. The 10% Ti-doped InO TFT had a field-effect mobility $1.03\;cm^2/V{\cdot}S$, a threshold voltage of 1.87 V, an on/off current ration grater than $10^7$, and a subthreshold slop of 0.67 V/dec.