• Journal of Power Electronics
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• v.15 no.4
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• pp.899-909
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• 2015

A dual-input boost-buck converter with coupled inductors (DIBBC-CI) is proposed as a thermoelectric generator (TEG) power conditioner with a wide input voltage range. The DIBBC-CI is built by cascading two boost cells and a buck cell with shared inverse coupled filter inductors. Low current ripple on both sides of the TEG and the battery are achieved. Reduced size and power losses of the filter inductors are benefited from the DC magnetic flux cancellation in the inductor core, leading to high efficiency and high power density. The operational principle, impact of coupled inductors, and design considerations for the proposed converter are analyzed in detail. Distributed maximum power point tracking, battery charging, and output control are implemented using a competitive logic to ensure seamless switching among operational modes. Both the simulation and experimental results verify the feasibility of the proposed topology and control.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.9
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• pp.932-940
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• 2011

This paper presents an integrated analysis of supply chain and financing decisions of multi-national corporation. We construct a model in which multiple currency storage units are installed to manage the currency flows associated with multi-national supply chain activities such as raw material procurement, process operation, inventory control, transportation and finished product sales. Core contribution of this study is to quantitatively investigate the influence of macroscopic economic factors such as exchange rates and taxes on operational decisions. The supply chain is modeled by the Process-Storage Network with recycle streams. The objective function of the optimization is minimizing the opportunity costs of annualized capital investments and currency/material inventories minus the benefit to stockholders interpreted by home currency. The major constraints of the optimization are that the material and currency storage units must not be depleted. A production and inventory analysis formulation, the periodic square wave (PSW) model, provides useful expressions for the upper/lower bounds and average levels of the currency and material inventory holdups. The expressions for the Kuhn-Tucker conditions of the optimization problem are reduced to a subproblem and analytical lot sizing equations. The procurement, production, transportation and financial transaction lot sizes can be determined by analytical expressions after the average flow rates are already known. We show that, when corporate income tax is taken into consideration, the optimal production lot and storage sizes are smaller than is the case when such factors are not considered typically by 20 %.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.12
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• pp.469-478
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• 2017

The mutual exclusion is originally based on the theory of race condition prevention in symmetric multi-processor operating systems. But recently, due to the generalization of multi-core processors, its application range has been rapidly shifted to parallel processing application domain. POSIX thread, WIN32 thread, and Java thread, which are typical parallel processing application development environments, provide a unique mutual exclusion mechanism for each of them. Applications that are very sensitive to performance in these environments may want to reduce the burden of mutual exclusion, even at some cost, such as inconvenience of coding. In this study, we implement Dekker's and Peterson's algorithm in the form of busy-wait and processor-yield in various platforms, and compare the performance of them with the built-in mutual exclusion mechanisms to evaluate the usability of the classic algorithms. The analysis result shows that Dekker's algorithm of processor-yield type is superior to the built-in mechanisms in POSIX and WIN32 thread environments at least 2 times and up to 70 times, and confirms that the practicality of the algorithm is sufficient.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.8
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• pp.261-270
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• 2014

As Internet traffic increases recently, much effort has been put on improving the performance of a web server. In addition to hardware side solutions such as replacement by high-end hardware or expansion of the number of servers, there are software side solutions to improve performance. Recent studies on these software side solutions have been actively performed. In this paper, we identify performance degradation problems occurring in a conventional TCP networking reception process and propose a way to solve them. We improve performance by combining three kinds of existing methods for Linux Networking Performance Improvement and two kinds of newly proposed methods in this paper. The three existing methods include 1) an allocation method of a packet flow to a core in a multi-core environment, 2) ITR(Interrupt Throttle Rate) method to control excessive interrupt requests, and 3) sk_buff data structure recycling. The two newly proposed methods are fd data structure recycling and epoll_event data structure recycling. Through experiments in a web server environment, we verify the effect of our two proposed methods and its combination with the three existing methods for performance improvement, respectively. We use three kinds of web servers: a simple web server, Lighttpd generally used in Linux, and Apache. In a simple web server environment, fd data structure recycling and epoll_event data structure recycling bring out performance improvement by about 7 % and 6%, respectively. If they are combined with the three existing methods, performance is improved by up to 40% in total. In a Lighttpd and an Apache web server environment, the combination of five methods brings out performance improvement by up to 36% and 20% in total, respectively.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.40 no.4
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• pp.183-190
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• 2017

This paper proposes a dynamic magnetic field emulator (DMFE), which can electrically emulate information for the magnetic stripes of most widely used credit cards. Payment transactions with most common credit cards are performed by reading the card's information, encoded in magnetic stripes, using the reader head of a point-of-sale (POS) system. A stripe-type permanent magnet is attached to the back side of the credit card, and information for payments or value-added service is reorganized by exposing it to strong magnetic field. The process of data recording and retrieving as stated above has been pointed out as a major cause of illegal credit card use, because the information on the magnetic stripe is always exposed, and is thus vulnerable to forgery or alteration. A dynamic magnetic field emulator displays card information only when necessary by using the principle of solenoidal magnets. The DMFE proposed in this paper can prevent fraudulent use if it is operated with a device, like a smart phone, or a separate user-authentication procedure. In addition, because it is possible to display various information as needed, it can be utilized for a smart multi-card application, in which information for multiple cards is stored in one card, and can be selected and used as needed. This paper introduces the necessity of the DMFE and its manufacturing principles. As a result, this study will be helpful for making various application cases in payment, which is a core area of the Fintech (a newly-coined word of finance and technology) industry.

• Journal of the Korea Society for Simulation
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• v.27 no.3
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• pp.1-11
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• 2018

Discrete event system specification (DEVS) has been used in many simulations including hybrid systems featuring both discrete and continuous behavior that require a lot of time to get results. Therefore, in this study, we proposed the acceleration of a DEVS-based hybrid system simulation using multi-cores and GPUs tightly coupled computing. We analyzed the proposed heterogeneous computing of the simulation in terms of the configuration of the target device, changing simulation parameters, and power consumption for efficient simulation. The result revealed that the proposed architecture offers an advantage for high-performance simulation in terms of execution time, although more power consumption is required. With these results, we discovered that our approach is applicable in hybrid system simulation, and we demonstrated the possibility of optimized hardware distribution in terms of power consumption versus execution time via experiments in the proposed architecture.

• The KIPS Transactions:PartC
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• v.15C no.2
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• pp.93-102
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• 2008

The network weather map and bandwidth time-series graph are popularly used to understand the current and past traffic condition of NSP, ISP, and enterprise networks. These systems collect traffic performance data from a SNMP agent running on the network devices such as routers and switches, store the gathered information into a DB, and display the network performance status in the form of a time-series graph or a network weather map using Web user interface. Most of current enterprise networks are constructed in the form of a hierarchical tree-like structure with multi-Gbps Ethernet links, which is quietly different from the national or world-wide backbone network structure. This paper focuses on the network weather map for current enterprise network. We start with the considering points in developing a network weather map system suitable for enterprise network. Based on these considerings, this paper proposes the best way of using SNMP in constructing a network weather map system. To prove our idea, we designed and developed a network weather map system for our campus network, which is also described in detail.

• Smart Structures and Systems
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• v.25 no.2
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• pp.241-254
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• 2020

Using confined shape memory alloy (SMA) bar or plate, this study proposes an innovative self-centering damper. The damper is essentially properly machined SMA core, i.e., bar or plate, that encased in buckling-restrained device. To prove the design concept, cyclic loading tests were carried out. According to the test results, the damper exhibited desired flag-shape hysteretic behaviors upon both tension and compression actions, although asymmetric behavior is noted. Based on the experimental data, the hysteretic parameters that interested by seismic applications, such as the strength, stiffness, equivalent damping ratio and recentering capacity, are quantified. Processed in the Matlab/Simulink environment, a preliminary evaluation of the seismic control effect for this damper was conducted. The proposed damper was placed at the first story of a multi-story frame and then the original and controlled structures were subjected to earthquake excitations. The numerical outcome indicated the damper is effective in controlling seismic deformation demands. Besides, a companion SMA damper which represents a popular type in previous studies is also introduced in the analysis to further reveal the seismic control characteristics of the newly proposed damper. In current case, it was found that although the current SMA damper shows asymmetric tension-compression behavior, it successfully contributes comparable seismic control effect as those having symmetrical cyclic behavior. Additionally, the proposed damper even shows better global performance in controlling acceleration demands. Thus, this paper reduces the concern of using SMA dampers with asymmetric cyclic behavior to a certain degree.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• Nuclear Engineering and Technology
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• v.55 no.2
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• pp.595-602
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• 2023

The EAST ICRF system operating space has been extended in power and phase control with a low-level RF system for the new double-strap antenna. Then the multi-step power and periodic phase scanning experiment were conducted in L-mode plasma, respectively. In the power scanning experiment, the stored energy, radiation power, plasma impedance and the antenna's temperature all have positive responses during the short ramp-ups of P_L;ICRF. The core ion temperature increased from 1 keV to 1.5 keV and the core heating area expanded from |Z| ≤ 5 cm to |Z| ≤ 10 cm during the injection of ICRF waves. In the phasing scanning experiment, in addition to the same conclusions as the previous relatively phasing scanning experiment, the superposition effect of the fluctuation of stored energy, radiation power and neutron yield caused by phasing change with dual antenna, resulting in the amplitude and phase shift, was also observed. The active control of RF output facilitates the precise control of plasma profiles and greatly benefits future experimental exploration.