• Journal of Broadcast Engineering
• /
• v.20 no.3
• /
• pp.388-397
• /
• 2015

High Efficiency Video Coding (HEVC)/H.265 is a new video coding standard which is known as high compression ratio compared to the previous standard, Advanced Video Coding (AVC)/H.264. Due to achievement of high efficiency, HEVC sacrifices the time complexity. To apply HEVC to the market applications, one of the key requirements is the fast encoding. To achieve the fast encoding, exploiting thread-level parallelism is widely chosen mechanism since multi-threading is commonly supported based on the multi-core computer architecture. In this paper, we implement both the Tile-level parallelism and the Frame-level parallelism for HEVC encoding on multi-core platform. Based on the implementation, we present two approaches in combining the Tile-level parallelism with Frame-level parallelism. The first approach creates the fixed number of tile per frame while the second approach creates the number of tile per frame adaptively according to the number of frame in parallel and the number of available worker threads. Experimental results show that both improves the parallel scalability compared to the one that use only tile-level parallelism and the second approach achieves good trade-off between parallel scalability and coding efficiency for both Full-HD (1080 x 1920) and 4K UHD (3840 x 2160) sequences.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.11 no.6
• /
• pp.325-334
• /
• 2016

Recently, Open Computing Language (OpenCL) has been proposed to provide a framework that supports heterogeneous computing platforms. By using an OpenCL framework, digital communication systems can support various protocols in a unified computing environment to achieve both high portability and high performance. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes for China Multimedia Mobile Broadcasting (CMMB) on a heterogeneous platform. Each step of LDPC decoding has different parallelization characteristics. In this paper, steps suitable for task-level parallelization are executed on the CPU, and steps suitable for data-level parallelization are processed by the GPU. To improve the performance of the proposed OpenCL kernels for LDPC decoding operations, explicit thread scheduling, loop-unrolling, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance by using heterogeneous multi-core processors on a unified computing framework.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.11 no.1
• /
• pp.27-35
• /
• 2015

Increasing the number of GPU (Graphic Processor Unit) cores, the studies on High Performance Computing Platform using GPU have actively been made in recent. This trend has led to the development of GPGPU (General Purpose GPU) and CUDA (Compute Unified Device Architecture) Framework. In this paper, we explain the many benefits of the GPU based system, and propose the ICIDF(Identify Compute-Intensive Data set and Function) methodology to apply GPU technology to legacy military information system for performance improvement. To demonstrate the efficiency of this methodology, we applied this method to AES CPU based program obtained from the Internet web site. Simply changing the data structure made improved the performance of AES program. As a result, the performance of AES based GPU program is improved gradually up to 10 times. Depending on the developer's ability, additional performance improvement can be expected. The problem to be solved is heat issue, but this problem has been much improved by the development of the cooling technology.

• Journal of Institute of Control, Robotics and Systems
• /
• v.16 no.7
• /
• pp.646-654
• /
• 2010

This paper describes an integrated chassis control for a maneuverability, a lateral stability and a rollover prevention of a vehicle by the using of the ESC and AFS. The integrated chassis control system consists of a supervisor, control algorithms and a coordinator. From the measured and estimation signals, the supervisor determines the vehicle driving situation about the lateral stability and rollover prevention. The control algorithms determine a desired yaw moment for lateral stability and a desired longitudinal force for the rollover prevention. In order to apply the control inputs, the coordinator determines a brake and active front steering inputs optimally based on the current status of the subject vehicle. To improve the reliability and to reduce the operating load of the proposed control algorithms, a multi-core ECU platform is used in this system. For the evaluation of this system, a closed loop simulations with driver-vehicle-controller system were conducted to investigate the performance of the proposed control strategy.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.11
• /
• pp.1707-1712
• /
• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.13 no.4
• /
• pp.141-151
• /
• 2017

Nowadays, It is undeniable that the threat of network security is growing as time flows due to worldwide development of wire/wireless, various Internet platform and sophisticated hacking techniques. The amount of traffics that Network security solution has to handle is increasing and recently many occurrence of explosive traffic attacks from PulseWave are being observed which has many similar characteristics to New DDos. Medium and small sized firms abroad have developed and distributed Snort and Suricata that are based on open-source Intrusion Detection System(IDS) / Intrusion Prevention System (IPS). The goal of this study is to compare between Windows7 by applying suicata 4.0.0 32bit version and Ubuntu 16.04.3 LTS by applying suicata 4.0.0 version which is an open source Intrusion Detection System / Intrusion Protection System that uses multi threads method. This experiment's environment was set as followed C1100 server model of Dell, Intel Xeon CPU L5520 2.27GHz*2 with 8 cores and 16 threads, 72GB of RAM, Samsung SSD 250GB*4 of HDD which was set on RAID0. According to the result, Suricata in Ubuntu is superior to Suricata in Windows7 in performance and this result indicates that Ubuntu's performance is far advanced than Windows7. This meaningful result is derived because Ubuntu that applied Suricata used multi core CPU and RAM more effectively.

• The Journal of the Acoustical Society of Korea
• /
• v.28 no.7
• /
• pp.589-598
• /
• 2009

As mobile devices become multi-functional, and converge into a single platform, there is a strong need for a codec that is able to provide consistent quality for speech and music content MPEG-D USAC standardization activities started at the 82nd MPEG meeting with a CfP and approved WD3 at the 88th MPEG meeting. MPEG-D USAC is converged technology of AMR-WB+ and HE-AAC V2. Specifically, USAC utilizes three core codecs (AAC ACELP and TCX) for low frequency regions, SBR for high frequency regions and the MPEG Surround tool for stereo information. USAC can provide consistent sound quality for both speech and music content and can be applied to various applications such as multi-media download to mobile device Digital radio Mobile TV and audio books.

• KNOM Review
• /
• v.23 no.2
• /
• pp.29-41
• /
• 2020

Networks are growing faster than ever before causing a multi-domain complexity. The diversity, variety and dynamic nature of network traffic and services require enhanced orchestration and management approaches. While many standard orchestrators and network operators are resulting in an increase of complexity for handling E2E slice orchestration. Besides, there are multiple domains involved in E2E slice orchestration including access, edge, transport and core network each having their specific challenges. Hence, handling of multi-domain, multi-platform and multi-operator based networking environments manually requires specified experts and using this approach it is impossible to handle the dynamic changes in the network at runtime. Also, the manual approaches towards handling such complexity is always error-prone and tedious. Hence, this work proposes an automated and abstracted solution for handling E2E slice orchestration using an intent-based approach. It abstracts the domains from the operators and enable them to provide their orchestration intention in the form of high-level intents. Besides, it actively monitors the orchestrated resources and based on current monitoring stats using the machine learning it predicts future utilization of resources for updating the system states. Resulting in a closed-loop automated E2E network orchestration and management system.

• Journal of Broadcast Engineering
• /
• v.17 no.3
• /
• pp.503-518
• /
• 2012

In this paper, we propose a complexity-based parallelization method of the sample adaptive offset (SAO) algorithm which is one of HEVC in-loop filters. The SAO algorithm can be regarded as region-based process and the regions are obtained and represented with a quad-tree scheme. A offset to minimize a reconstruction error is sent for each partitioned region. The SAO of the HEVC can be parallelized in data-level. However, because the sizes and complexities of the SAO regions are not regular, workload imbalance occurs with multi-core platform. In this paper, we propose a LCU-based SAO algorithm and a complexity prediction algorithm for each LCU. With the proposed complexity-based LCU processing, we found that the proposed algorithm is faster than the sequential implementation by a factor of 2.38 times. In addition, the proposed algorithm is faster than regular parallel implementation SAO by 21%.

• Journal of Internet Computing and Services
• /
• v.22 no.6
• /
• pp.129-140
• /
• 2021

The next generation mBcN should be built to cooperate with the wireless network to support hyper-speed and hyper-connectivity. In this paper, we propose a network architecture for the cooperation mBcN and 5G commercial network and architecture of the cooperative security gateway required for the cooperation. The proposed cooperative security gateway is between gNB and UPF to support LBO, SFC, and security. Our analysis shows that the proposed architecture has several advantages. First of all, user equipment connected with the mBcN can be easily connected through the 5G commercial radio network to the mBcN. Second, the military application traffic can be transmitted to mBcN without going through the 5G core network, reducing the end-to-end transmission delay without causing the traffic load on the 5G core network. In addition, the security level of the military application can effectively be maintained because the user equipment can be connected to the cooperative security gateway, and the traffic generated by the user equipment is transmitted to the mBcN without going through the 5G core network. Finally, we demonstrate that LBO, SFC, and security modules are essential functions of the proposed gateway in the 5G test-bed environment.