• Journal of KIISE
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• v.42 no.2
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• pp.177-182
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• 2015

The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.

• Journal of KIISE
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• v.44 no.5
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• pp.469-475
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• 2017

The emerging NVMe-based multi-queue SSDs provides a high bandwidth by parallel I/O, i.e., each core performs I/O through its dedicated queue in parallel with other cores. To provide a bandwidth share for each application with I/O, a fair-share scheduler that provides a bandwidth share to each core is required. In this study, we proposed a multi-core scalable fair-queuing algorithm for multi-queue SSDs. The algorithm adopts randomization to minimize the inter-core synchronization overheads and provides a weight-proportional bandwidth share to each core. The results of our experiments indicated that the proposed algorithm gives accurate bandwidth partitioning and outperforms the existing FlashFQ scheduler, regardless of the number of cores for a Linux kernel with block-mq.

• Journal of IKEEE
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• v.19 no.3
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• pp.357-365
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• 2015

Recently, embedded systems such as aircraft and automobilie, are developed as modular architecture instead of federated architecture because of SWaP(Size, Weight and Power) issues. In addition, partition operating system that support multiple logical node based on partition concept were recently appeared. Distributed recovery block is fault tolerance design scheme that applicable to mission critical real-time system to support real-time take over via real-time synchronization between participated nodes. Because of real-time synchronization, single-core based computer is not suitable for partition based distributed recovery block design scheme. Multi-core and AMP(Asymmetric Multi-Processing) based partition architecture is required to apply distributed recovery block design scheme. In this paper, we proposed design scheme of distributed recovery block on the multi-core based supervised-AMP architecture partition operating system. This paper implements flight control simulator for avionics to check feasibility of our design scheme.

• Journal of Korea Multimedia Society
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• v.22 no.7
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• pp.759-769
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• 2019

Since a surgery simulation should be able to represent the internal structure of the human body, it is advantageous to adopt volume based techniques rather than polygon based techniques. However, the volume based techniques induce large computation to deform heterogeneous volume datasets such as bones and muscles. In this study, we propose a new method to deform volume data using multi-core CPUs. By improving previous studies, the proposed method minimizes unnecessary propagation operations. Moreover, we propose an efficient task-partitioning method for volume deformation using multi-core CPUs. As a result, we can simulate the deformation of heterogeneous volume data at an interactive speed without special hardware.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.1-8
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• 2019

Recently, avionics has been migrating from a federated architecture to an integrated modular architecture based on a multi-core to reduce the number of systems, weight, power consumption, and platform redundancy. The volume of data which must bo provided to the pilot through the display device has increased, because an integrated single device performs multiple functions. For this reason, the volume of data processed by the graphic processor within a fixed operation period has increased. In this paper, we provide a multi-core-based rendering engine in to perform more graphics processing within a fixed operation period. We assume the proposed method uses a multi-core-based partitioning operating system using the AMP (Asymmetric Multi-Processing) architecture.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.747-748
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• 2008

In this paper, we propose a new algorithm for task scheduling consisting of subtask partitioning and subtask priority scheduling steps in order to keep the peak power under the system specification. The subtask partitioning stepis performed to minimize the idle operation time for processors by dividing a task into multiple subtasks using the least square method developed with power consumption pattern of tasks. In the subtask priority scheduling step, a priority is assigned to a subtask based on the power requirement and the power variation of subtask so that the peak power violation can be minimized and the task can be completed within the execution time deadline.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.3
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• pp.3-9
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• 2011

In this paper, we propose workload partitioning methods in parallelizing AES-CCM which is proposed as the wireless encryption and message integrity standard IEEE 802.11i. In parallelizing AES-CCM having data dependency, synchronizations among processors are required, and multi-core processors have a very large range of synchronization performance. We propose and compare the performance of various workload partitioning methods by considering both the computational characteristics of AES-CCM and the synchronization overhead.

• KIISE Transactions on Computing Practices
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• v.21 no.4
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• pp.315-319
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• 2015

This paper addresses the design and implementation of an Android application for real-time precise motion control. To provide stable real-time performance, we implemented the application in two parts: Android service in the form of a daemon process, which periodically transfers a set of position commands for all motors through a real-time fieldbus, and Android UI application, which generates and delivers the set of position commands to the Android service. To support such a real-time motion control application, we use multi-core partitioning, which partitions the processor cores into a real-time partition to be used by the real-time motion control service and a non-real-time partition to be used by the Android application, and set up a shared buffer between them for communication. Our experiments show that we can obtain a motion control period of 2 ms with 99% task activation jitters less than ${\pm}55{\mu}s$ for a configuration where each of the four threads controls two motors in a group.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.57-64
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• 2019

Recently, avionics systems are being developed as integrated modular architecture applying the modular integration design of the functional unit to reduce maintenance costs and increase operating performance. Additionally, a partitioning operating system based on virtualization technology was used to process various mission control functions. In virtualization technology, the CPU processing load distribution is a key consideration. Especially, the uncertainty of the I/O processing time is a risk factor in the design of reliable avionics systems. In this paper, we examine the influence of the I/O processing method by comparing and analyzing the CPU processing load by the I/O processing method through use of case analysis and applying it to the example of spatial-temporal partitioning.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.43-53
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• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.