• Title/Summary/Keyword: multi-core architecture

Search Result 158, Processing Time 0.027 seconds

Thermal Analysis of 3D Multi-core Processors with Dynamic Frequency Scaling (동적 주파수 조절 기법을 적용한 3D 구조 멀티코어 프로세서의 온도 분석)

  • Zeng, Min;Park, Young-Jin;Lee, Byeong-Seok;Lee, Jeong-A;Kim, Cheol-Hong
    • Journal of the Korea Society of Computer and Information
    • /
    • v.15 no.11
    • /
    • pp.1-9
    • /
    • 2010
  • As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

Application of Multi-Purposed Emotional Space for Renewing Idle Spaces around Core Cultural Facilities - Focused on the National Asian Culture Complex - (거점 문화시설 인근 유휴공간의 재생을 위한 다목적 감성공간 적용 - 국립 아시아문화전당을 대상으로 -)

  • Kim, Seulki;Han, Seung-Hoon
    • KIEAE Journal
    • /
    • v.16 no.1
    • /
    • pp.103-110
    • /
    • 2016
  • Purpose: This study suggests the multi-purposed emotional space that is one of the alternatives to reuse idle spaces in the city. Because human who is living in modern society begins pursue new contents and leisurely life all the time and live toward the period of high emotion with personal characteristics, architectural industry also need to change its planning and design to satisfy contemporary man and to adjust rapid social mobility. Method: For this study, the buildings where are located near Asia Cultural Complex (ACC) and leaved as idle spaces now that is used for important facilities are used to apply the multi-purposed emotional Space. Essential methodology and terminology were examined to estimate and construct the multi-purposed emotional space. Result: The multi-purposed emotional space provides that people aggressively request subjects to satisfy their emotional attractiveness as well as comforts and pleasures beyond the functional basic requirements in space. On the other words, it can be regarded as limited context to physical space responsive to social and environmental changes for the surrounding, and may maximize user experiences. Since emotions tend to be abstract and subjective while architectural space has pretty physical properties, this study attempts to integrate contrastive properties between emotional and architectural spaces to make a real object.

Development of a Multi-Layered Workflow Management System for Product Development Processes (제품 개발 프로세스 관리를 위한 다층 통합 워크플로우 시스템 개발)

  • 강석호;김영호;김동수;배준수;배혜림
    • Korean Management Science Review
    • /
    • v.16 no.1
    • /
    • pp.187-201
    • /
    • 1999
  • In this paper, we propose a multi-layered architecture of workflow management systems based on CORBA (Common Object Request Broker Architecture). The system aims to support product development processes in distributed environment. Many companies have started to adopt workflow management systems to manage and support their business processes. However, there are many problems in direct application of those systems to product development environments. These mainly resulted from the dynamic features of product development processes. It is strongly required to support dynamic processes as well as static and procedural ones in an integrated and consistent manner. To meet these requirements, a basic workflow management system has been developed as the core component of the integrated architecture. This performs the basic functions of workflow management system. Second, a dynamic workflow management system based on a bidding mechanism has been developed to manage processes that cannot be easily defined or are likely to be modified, Finally, an SGML workflow management system, which is the third layer in the architecture, has been developed to manage documents processing workflows by integration SGML documents contents and process information into the structured SGML document.

  • PDF

A Task Scheduling Strategy in a Multi-core Processor for Visual Object Tracking Systems (시각물체 추적 시스템을 위한 멀티코어 프로세서 기반 태스크 스케줄링 방법)

  • Lee, Minchae;Jang, Chulhoon;Sunwoo, Myoungho
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.24 no.2
    • /
    • pp.127-136
    • /
    • 2016
  • The camera based object detection systems should satisfy the recognition performance as well as real-time constraints. Particularly, in safety-critical systems such as Autonomous Emergency Braking (AEB), the real-time constraints significantly affects the system performance. Recently, multi-core processors and system-on-chip technologies are widely used to accelerate the object detection algorithm by distributing computational loads. However, due to the advanced hardware, the complexity of system architecture is increased even though additional hardwares improve the real-time performance. The increased complexity also cause difficulty in migration of existing algorithms and development of new algorithms. In this paper, to improve real-time performance and design complexity, a task scheduling strategy is proposed for visual object tracking systems. The real-time performance of the vision algorithm is increased by applying pipelining to task scheduling in a multi-core processor. Finally, the proposed task scheduling algorithm is applied to crosswalk detection and tracking system to prove the effectiveness of the proposed strategy.

Parallelizing Feature Point Extraction in the Multi-Core Environment for Reducing Panorama Image Generation Time (파노라마 이미지 생성시간을 단축하기 위한 멀티코어 환경에서 특징점 추출 병렬화)

  • Kim, Geon-Ho;Choi, Tai-Ho;Chung, Hee-Jin;Kwon, Bom-Jun
    • Journal of KIISE:Computing Practices and Letters
    • /
    • v.14 no.3
    • /
    • pp.331-335
    • /
    • 2008
  • In this paper, we parallelized a feature point extraction algorithm to reduce panorama image generation time in multi-core environment. While we compose a panorama image with several images, the step to extract feature points of each picture is needed to find overlapped region of pictures. To perform rapidly feature extraction stage which requires much calculation, we developed a parallel algorithm to extract feature points and examined the performance using CBE(Cell Broadband Engine) which is asymmetric multi-core architecture. As a result of the exam, the algorithm we proposed has a property of linear scalability-the performance is increased in proportion the number of processors utilized. In this paper, we will suggest how Image processing operation can make high performance result in multi-core environment.

Applying scheduling techniques for improving the performance of network equipment network subsystem (네트워크 장비 성능 향상을 위한 네트워크 서브시스템 스케줄링 기법 적용)

  • Bae, Byoungmin;Kim, MinJung;Lee, GowangLo;Jung, YungJoon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2013.05a
    • /
    • pp.65-67
    • /
    • 2013
  • The recent high-performance network equipment is required, and also require high network bandwidth utilization. It is a trend to develop increasingly using multi-core processors for high-performance network servers. Propose a method to improve the performance of the network sub-system, considering the characteristics of multi-core as a way to improve these high-performance and high network throughput. In this paper, we confirm through experiments on how to improve the communication performance, optimize performance and take full advantage of multi-core by Network communication process to improve the performance of the multi-core processor architecture, the process of concentration, the overhead for each core, based on network traffic according to the interrupt affinity in this process to determine the optimal core to give. The experiments were implemented in the Linux kernel, and experiments to improve the network throughput up to 30%, bringing reduces the Linux communication process to improve the performance of the processor overhead of up to 10%.

  • PDF

User Experience Assisted Energy-Efficient Software Design for Mobile Devices on the big.LITTLE Core Architecture (사용자 경험을 기반으로 big.LITTLE 멀티코어 구조의 스마트 모바일 단말의 에너지 소비를 최적화 하는 소프트웨어 구조 설계)

  • Lim, Sung-Hwa
    • Journal of the Semiconductor & Display Technology
    • /
    • v.19 no.1
    • /
    • pp.23-28
    • /
    • 2020
  • In Smart mobile devices embedding big.LITTLE architectures, the conventional multi-core assignment scheme for user applications may incur wasteful energy consumption and long response time. In this paper, we propose a user experience assisted energy-efficient multicore assignment scheme. Our simulation results show that the proposed scheme achieves at 40% less energy consumption and at 20% less response time comparing to the legacy scheme.

A study on an efficient prediction of welding deformation for T-joint laser welding of sandwich panel Part II : Proposal of a method to use shell element model

  • Kim, Jae Woong;Jang, Beom Seon;Kang, Sung Wook
    • International Journal of Naval Architecture and Ocean Engineering
    • /
    • v.6 no.2
    • /
    • pp.245-256
    • /
    • 2014
  • I-core sandwich panel that has been used more widely is assembled using high power $CO_2$ laser welding. Kim et al. (2013) proposed a circular cone type heat source model for the T-joint laser welding between face plate and core. It can cover the negative defocus which is commonly adopted in T-joint laser welding to provide deeper penetration. In part I, a volumetric heat source model is proposed and it is verified thorough a comparison of melting zone on the cross section with experiment results. The proposed model can be used for heat transfer analysis and thermal elasto-plastic analysis to predict welding deformation that occurs during laser welding. In terms of computational time, since the thermal elasto-plastic analysis using 3D solid elements is quite time consuming, shell element model with multi-layers have been employed instead. However, the conventional layered approach is not appropriate for the application of heat load at T-Joint. This paper, Part II, suggests a new method to arrange different number of layers for face plate and core in order to impose heat load only to the face plate.

A Study on GPGPU Performance Improvement Technique on GCN Architecture Using OpenCL API (GCN 아키텍쳐 상에서의 OpenCL을 이용한 GPGPU 성능향상 기법 연구)

  • Woo, DongHee;Kim, YoonHo
    • The Journal of Society for e-Business Studies
    • /
    • v.23 no.1
    • /
    • pp.37-45
    • /
    • 2018
  • The current system upon which a variety of programs are in operation has continuously expanded its domain from conventional single-core and multi-core system to many-core and heterogeneous system. However, existing researches have focused mostly on parallelizing programs based CUDA framework and rarely on AMD based GCN-GPU optimization. In light of the aforementioned problems, our study focuses on the optimization techniques of the GCN architecture in a GPGPU environment and achieves a performance improvement. Specifically, by using performance techniques we propose, we have reduced more then 30% of the computation time of matrix multiplication and convolution algorithm in GPGPU. Also, we increase the kernel throughput by more then 40%.