• Journal of Advanced Navigation Technology
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• v.11 no.4
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• pp.408-414
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• 2007

Research advances in the areas of micro-sensor device and wireless network technology, has made it possible to develop energy efficient and low cost wireless sensor nodes. In this paper, the forward error control (FEC) scheme for lower power consumption and excellent BER(Bit Error Rate) performance during transmission propose in multi-hop wireless sensor network based on FSK modem. The FEC technique uses extra processing power related to encoding and decoding, it is need complex functions to be built into the sensor node. The probability of receiving a correct bit and codeword for relaying a frame over h nodes to the sink node is calculated as a function of channel parameter, number of hops, number of bits transmitted and the distance between the different nodes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.315-323
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• 1987

Generally, general-purpose image processing system is so expensive that not so many users easily can access the system. In this paper attemps have been made to design and describe a general and economical image processing system for real-time aplications such as image data compression, pattern recognition and target tracking. The system comprises an operator console, image data acquisition/display sistem and IBM PC/XT. The system also utilizes a high speed Fairchild 16-bit microprocessor with ALU speed of 375 nsec for system control, algrithm execution and user computation. The system also can digitize /display a 256x 256x 8 bit image in real time and store two frames of images. All image pixels are directly accessible by the microprocessor for fast and efficient computation. Some experimental and illustrative results such as target tracking are presented to show the efficient performance of the system.

• Journal of the Korea Society for Simulation
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• v.11 no.2
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• pp.17-29
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• 2002

There is an increasing interest in high-performance A/D(Analog-to-Digital) converters for use in integrated analog and digital mixed processing systems. Pipeline A/D converter architectures coupled with BiCMOS process technology have the potential for realizing monolithic high-speed and high-accuracy A/D converters. In this paper, the design of 12bit pipeline BiCMOS A/D converter presented. A BiCMOS operational amplifier and comparator suitable for use in the pipeline A/D converter. Test/simulation results of the circuit blocks and the converter system are presented. The main features is low distortion track-and-hold with 0-300MHz input bandwidth, and a proprietary 12bit multi-stage quantizer. Measured value is DNL=${\pm}$0.30LSB, INL=${\pm}$0.52LSB, SNR=66dBFS and SFDR=74dBc at Fin=24.5MHz. Also Fabricated on 0.8um BiCMOS process.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.395-402
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• 2002

In the conventional public switched telephone network(PSTN), there are various types of modulation that can be used in ADSL to offer fast data communication, two of which are CAP(Carrierless Amplitude Phase) and DMT(Discrete MultiTone). As we consider the current situation, DMT is getting more predominant in the market than CAP. One of the reasons is that it gives high performance in spite of its high complexity Since DMT divides the full range of bandwidth into 256 sub-channels, it can be highly adaptive in the circumstances, where the problems of attenuation and noise caused by the propagation distance are very crucial. In this paper, a new bit loading algorithm for DMT modulation is proposed. The proposed algorithm can be efficiently implemented in a way that it requires less computation than the conventional modulation techniques. In contrast to the conventional algorithms which perform sorting processing, the proposed algorithm uses look-up tables to reduce the repetition of calculation. Consequently, it is shown that less processing time and lower complexity can be achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9C
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• pp.721-728
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• 2010

CAMC (constant amplitude multi-code) has a better performance of error correction in iterative decoding than SPCPC (single parity check product code). CAMC benefits from a processing gain since it belongs to a spread spectrum signal. We show that the processing gain enhances the performance of CAMC. Additional correction of bit errors is achieved in the de-spreading of iteratively decoded signal. If the number of errors which survived the iterative decoding is less than or equal to ($\sqrt{N}/2-1$), all of the bit errors are removed after the de-spreading. We also propose a stopping criterion in the iterative decoding, which is based on the histogram of EI (extrinsic information). The initial values of EI are randomly distributed, and then they converge to ($-E_{max}$) or ($+E_{max}$) over the iterations. The strength of the convergence reflects how successfully error correction process is performed. Experimental results show that the proposed method achieves a gain of 0.2 dB in Eb/No.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.426-433
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• 2008

In this paper, we present a method to improve the performance of the four transmit antenna quasi-orthogonal space-time block code (STBC) in the coded system. For the four transmit antenna case, the quasi-orthogonal STBC consists of two symbol groups which are orthogonal to each other, but intra group symbols are not. In uncoded system with the matched filter detection, constellation rotation can improve the performance. However, in coded systems, its gain is absorbed by the coding gain especially for lower rate code. We propose an iterative decoding method to improve the performance of quasi-orthogonal codes in coded systems. With conventional quasi-orthogonal STBC detection, the joint ML detection can be improved by iterative processing between the demapper and the decoder. Simulation results shows that the performance improvement is about 2dB at 1% frame error rate.

• ETRI Journal
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• v.40 no.5
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• pp.677-686
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• 2018

A novel data hiding technique based on modified histogram shifting that incorporates multi-bit secret data hiding is proposed. The proposed technique divides the image pixel values into embeddable and nonembeddable pixel values. Embeddable pixel values are those that are within a specified limit interval surrounding the peak value of an image. The limit interval is calculated from the number of secret bits to be embedded into each embeddable pixel value. The embedded secret bits can be perfectly extracted from the stego image at the receiver side without any overhead bits. From the simulation, it is found that the proposed technique produces a better quality stego image compared to other data hiding techniques, for the same embedding rate. Since the proposed technique only embeds the secret bits in a limited number of pixel values, the change in the visual quality of the stego image is negligible when compared to other data hiding techniques.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.145-148
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• 2000

This paper presents the performance of a GHICW(Group-wise Hybrid Interference Cancellation scheme based on Wiener filtering) receiver for the multi-rate DS-CDMA system. Our scheme has a small processing delay and a simple hardware complexity compared to ordinary interference cancellation schemes by grouping users with the same date rate. The performance improvement of the low rate user is obtained by using a Wiener filter which precisely estimates the high rate users' bit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.57-62
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• 2011

In this paper, an efficient architecture for MFVLD(Multi-Format Variable Length Decoder) which can process H.264, MPEG-2, MPEG-4, AVS, VC-1 bitstream is proposed. The proposed MF-VLD is designed to be adapted to the MPSOC (Multi-processor System on Chip) architecture, uses bit-plane algorithm for the processing of inverse quantized data to reduce the width of AHB bus. External SDRAM is used to minimize the internal memory size. In this architecture, the adding or removing each variable length decoder can be easily done by using multiplexor. The designed MF-VLD can be operated in 200MHz at 0.18um process. The gate size is 657K gate and internal memory size is 27Kbyte.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.9-12
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• 2001

In DS/CDMA system the number of output signal levels increases as multi-channel signals are summed, hence the power amplifier with high linearity is required. PW/CDMA is a transmission technique that performs pulse width modulation on the multilevel signal synthesized from multiple channel data. In PW/CDMA system the signal level is maintained to be binary, hence the modulation and demodulation circuits become simple. In this paper we derive the probability of bit error of the PW/CDMA system in AWGN environment. The results are compared with DS/CDMA system and are verified through the computer simulations.