• Nuclear Engineering and Technology
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• v.56 no.8
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• pp.3043-3066
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• 2024

In various small modular reactor (SMR) designs currently under development, the conventional concrete containment building has been replaced by a metal containment vessel (MCV). In these systems, the gap between the MCV and the reactor pressure vessel is filled with gas or vacuumed weakly, effectively suppressing conduction and convection heat transfer. However, thermal radiation remains the major mode of heat transfer during normal operation. The objective of this study was to investigate the heat-transfer mechanisms in integral pressurized water reactor (IPWR)-type SMRs under various gas-filled conditions using computational fluid dynamics. The use of thermal radiation shielding (TRS) with a much lower emissivity material than the MCV surface was also evaluated. The results showed that thermal radiation was always the dominant contributor to heat loss (48-97%), while the conjugated effects of the gas candidates on natural convection and thermal radiation varied depending on their thermal and radiative properties, including absorption coefficient. The TRS showed an excellent insulation performance, with a reduction in the total heat loss of 56-70% under the relatively low temperatures of the IPWR system, except for carbon dioxide (13%). Consequently, TRS can be utilized to enhance the thermal efficiency of SMR designs by suppressing the heat loss through the MCV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.4
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• pp.548-555
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• 2022

This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

• Journal of IKEEE
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• v.24 no.3
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• pp.901-908
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• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• Journal of IKEEE
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• v.25 no.4
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• pp.625-633
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• 2021

This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, N_PE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for N_PE=1 and N_PE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for N_PE=1 and 3.5 million times/sec for N_PE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).

• Journal of IKEEE
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• v.26 no.4
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• pp.736-741
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• 2022

Lattice-based cryptography is the most practical post-quantum cryptography because it enjoys strong worst-case security, relatively efficient implementation, and simplicity. Ring learning with errors (R-LWE) is a public key encryption (PKE) method of lattice-based encryption (LBC), and the most important operation of R-LWE is the modular polynomial multiplication of rings. This paper proposes a method for optimizing modular multipliers based on approximate computing (AC) technology, targeting the medium-security parameter set of the R-LWE cryptosystem. First, as a simple way to implement complex logic, LUT is used to omit some of the approximate multiplication operations, and the 2's complement method is used to calculate the number of bits whose value is 1 when converting the value of the input data to binary. We propose a total of two methods to reduce the number of required adders by minimizing them. The proposed LUT-based modular multiplier reduced both speed and area by 9% compared to the existing R-LWE modular multiplier, and the modular multiplier using the 2's complement method reduced the area by 40% and improved the speed by 2%. appear. Finally, the area of the optimized modular multiplier with both of these methods applied was reduced by up to 43% compared to the previous one, and the speed was reduced by up to 10%.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.189-192
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• 1991

This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2002.04a
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• pp.491-495
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• 2002

In the paper, a Visual factory model for a optical-components manufacturing process is built. The optical-components manufacturing process is composed of 3 operation processes; optical sub assembly process, package assembly process, and fiber assembly process. Each process is managed not a batch mode, which is one of most popular manufacturing styles to produce a great deal of industrial output, but though a modular cell. In the processes, a modular cell has to be processed independently of the other cells. Optimization for the composition of assembly cell in the optical-components system is made by the Visual factory model.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.3
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• pp.1-8
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• 2002

Modular Multiplication in Galois Field GF(2/sup m/) is a basic operation for many applications, particularly for public key cryptography. This paper presents a new architecture that can process modular multiplication on GF(2/sup m/) per m clock cycles using a cellular automata. Proposed architecture is more efficient in terms of the space and time than that of systolic array. Furthermore it can be efficiently used for the hardware design for exponentiation computation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.636-639
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• 2002

In the paper, a Visual factory model for a optical-components manufacturing process is built. The optical-components manufacturing process is composed of 3 operation processes; optical sub assembly process, package assembly process, and fiber assembly process. Each process is managed not a batch mode, which is one of most popular manufacturing styles to produce a great deal of industrial output, but though a modular cell. In the processes, a modular cell has to be processed independently of the other cells. Optimization for the composition of assembly cell in the optical-components system is made by the Visual factory model.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1189-1196
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• 2014

A modular multilevel-clamped composited multilevel converter ($M-MC^2$) is proposed. $M-MC^2$ enables topology reconfiguration, power device reuse, and composited clamping. An advanced five-level converter ($5L-M-MC^2$) is derived from the concept of $M-MC^2$. $5L-M-MC^2$ integrates dual three-level T-type modules and one three-level neutral point clamped module. This converter can also integrate dual three-level T-type modules and one passive diode module by utilizing the device reuse scheme. The operation principle and SPWM modulation are discussed to highlight converter performance. The proposed $M-MC^2$ is comprehensively compared with state-of-the-art five-level converters. Finally, simulations and experimental results are presented to validate the effectiveness of the main contributions of this study.