• Journal of IKEEE
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• v.24 no.4
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• pp.961-968
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• 2020

This paper describes a design of high performance modular multiplier that is essentially used for elliptic curve cryptography. Our modular multiplier supports modular multiplications for five field sizes over GF(p), including 192, 224, 256, 384 and 521 bits as defined in NIST FIPS 186-2, and it calculates modular multiplication in two steps with integer multiplication and reduction. The Karatsuba-Ofman multiplication algorithm was used for fast integer multiplication, and the Lazy reduction algorithm was adopted for reduction operation. In addition, the Nikhilam division algorithm was used for the division operation included in the Lazy reduction. The division operation is performed only once for a given modulo value, and it was designed to skip division operation when continuous modular multiplications with the same modulo value are calculated. It was estimated that our modular multiplier can perform 6.4 million modular multiplications per second when operating at a clock frequency of 32 MHz. It occupied 456,400 gate equivalents (GEs), and the estimated clock frequency was 67 MHz when synthesized with a 180-nm CMOS cell library.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.60-68
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• 1994

In this paper, the multiplicative algorithm of two polynomials over finite field GF(($p^{m}$) is presented. Using the presented algorithm, the multiple-valued multiplier of the serial input-output modular structure by CCD is constructed. This multiple-valued multiplier on CCD is consisted of three operation units: the multiplicative operation unit, the modular operation unit, and the primitive irreducible polynomial operation unit. The multiplicative operation unit and the primitive irreducible operation unit are composed of the overflow gate, the inhibit gate and mod(p) adder on CCD. The modular operation unit is constructed by two mod(p) adders which are composed of the addition gate, overflow gate and the inhibit gate on CCD. The multiple-valued multiplier on CCD presented here, is simple and regular for wire routing and possesses the property of modularity. Also. it is expansible for the multiplication of two elements on finite field increasing the degree mand suitable for VLSI implementation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.8
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• pp.1108-1114
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• 2013

This paper presents a new winding topology for MW class offshore wind generator having modular and dual 3-phase. Based on proposed simplified relationship between magnetic flux and phase current in the air gap, several new windings for modular and dual 3-phase are made. In case of one inverter operation or faulty operation, the proposed model can have balanced 3-phase induced voltage whereas the conventional generator with modular winding has unbalanced induced voltage, which can be important issue in offshore generator. The model was applied into 6MW prototype machine with dual 3-phase. Using finite element analysis, induced voltage, inductance were investigated. The results show that the proposed modular winding can be applicable to dual inverter system with electrically balanced voltage.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.2
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• pp.738-756
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• 2020

The modular multiplication is the key module of public-key cryptosystems such as RSA (Rivest-Shamir-Adleman) and ECC (Elliptic Curve Cryptography). However, the efficiency of the modular multiplication, especially the modular square, is very low. In order to reduce their operation cycles and power consumption, and improve the efficiency of the public-key cryptosystems, a dual-field efficient FIPS (Finely Integrated Product Scanning) modular multiplication algorithm is proposed. The algorithm makes a full use of the correlation of the data in the case of equal operands so as to avoid some redundant operations. The experimental results show that the operation speed of the modular square is increased by 23.8% compared to the traditional algorithm after the multiplication and addition operations are reduced about (s² - s) / 2, and the read operations are reduced about s² - s, where s = n / 32 for n-bit operands. In addition, since the algorithm supports the length scalable and dual-field modular multiplication, distinct applications focused on performance or cost could be satisfied by adjusting the relevant parameters.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.268-273
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• 2002

In this paper, a new parallel multiplier circuit over $GF(2^m)$ has been proposed. The new multiplier is composed of polynomial multiplicative operation part and modular arithmetic operation part, irreducible polynomial operation part. And each operation has modular circuit block. For design the new proposed circuit, it develop generalized equations using frame each operation idea and show a example for $GF(2^m)$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.10
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• pp.1672-1681
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• 2016

This paper proposes a wireless parallel operation method of three-phase modular UPS inverter using resistive droop control. Furthermore, it applies a virtual resistor to droop control so that the output impedance of UPS inverter gets closer to resistive. It makes resistive droop control effective. The simulation using PSIM was performed in order to verify the validity of proposed algorithm. After consisting two-parallel system with three-phase modular UPS inverter, the experiment according to resistive load was conducted. It demonstrated the performance of current sharing and power sharing.

• Journal of Convergence for Information Technology
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• v.8 no.5
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• pp.77-83
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• 2018

A modular robot that memorizes motion can be easily created and operated because it expresses by hand. However, since there is not enough storage space in the module to store the user-created operation, it is impossible to reuse the created operation, and when the modular robot again memorizes the operation, it changes to another operation. There is no main controller capable of operating a plurality of modular robots at the same time, and thus there is a disadvantage that the user must input directly to the modular robot. To overcome these disadvantages, a remote controller has been proposed that can be operated in the surrounding smart devices by designing web server and component based software using wired and wireless network. In the proposed method, various types of structures are created by connecting to a modular robot, and the reconstructed operation is performed again after storing, and the usefulness is confirmed by regenerating the stored operation effectively. In addition, the reliability of the downloaded trajectory data is verified by analyzing the difference between the trajectory data and the actual trajectory. In the future, the trajectory stored in the remote controller will be standardized using the artificial intelligence technique, so that the operation of the modular robot will be easily implemented.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.21 no.3
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• pp.110-117
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• 2022

A chiller cooler absorbs the thermal energy of water to generate cold water and supplies the generated cold water to a cold water pipe buried in the wall of a small mobile modular house to greatly increase the cooling area. An attempt was made to reduce the required cooling time significantly. A small chiller cooler suitable for the cooling load of a small mobile modular house with an area less than 3.3 m² was employed. When cooling is done during summer using a chiller cooler installed outdoors, heat absorption energy loss occurs in the cold water pipe owing to the high temperature. To address this, a study was conducted to reduce the endothermic energy loss significantly. As the mass flow rate of the cold water flowing inside the cold water pipe increased, the temperature decrease gradient of the cold water increased. From the start of the cooling operation, the air temperature of the small mobile modular house decreased linearly in proportion to the operation time. Furthermore, the temperature of the air inside the small mobile modular house decreased in proportion to the increase in the flow of water inside the cold water pipe.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.223-225
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• 2021

Modular multiplication is a key operation for point scalar multiplication of ECC, and is the most important factor affecting the performance of ECC processor. This paper describes a design of a 256-bit modular multiplier that adopts 3-way Toom-Cook multiplication algorithm and modified fast reduction algorithm. One 90-bit multiplier and three 264-bit adders were used to optimize the hardware size and the number of clock cycles required. The modular multiplier was verified by implementing it using Zynq UltraScale+ MPSoC device and the modular multiplication operation takes 15 clock cycles.