• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.95-102
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• 1996

This paper describes the realization of a rela-time adaptive acoustic echo canceller, which adopts a microprogramming method, for removing acoustical echoes in speakerphone systems using th eADSP-2101 microprocessor with a pipeline and modified harvard architecture. We apply the LMS (least mean square) algorithm to estimate the coefficients of a transversal FIR filter. For the acustic adaptive echo canceller, we propose a parallel operation programming to imrove algorithm execution speed and apply a nonlinear quantization to reduce the quantization error caused by large dynamic range of voice signal.