• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.57.1-57
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• 2001

The objectives of congestion control in ATM (Asynchronous Transfer Mode) networks are maximum utilization of network resources, acceptable level of low cell loss and fairness among all VCs (Virtual Connections). In this paper, we present a congestion control algorithm which is based on state space model, The proposed controller uses optimal control algorithms (LQR, Mixed-LQR), where control parameters can be designed to ensure the stability of the control loop in a control theoretic sense, over the propagation delay. We show how the control mechanism can be used to design a controller to support ABR service based on feedback of explicit rates. Simulation results are presented to substantiate our claim.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• Journal of the Korean Operations Research and Management Science Society
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• v.24 no.1
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• pp.49-58
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• 1999

A new channel access function is proposed to enhance the performance of the Joint CDMA/PRMA. It is obtained in consideration of the number of terminals in reservation mode and the number of terminals in contention mode whose probability distribution is estimated by applying pseudo Bayesian approach. Simulation results show that the performance of the Joint CDMA/PRMA can be improved by applying new channel access function under voice-only traffic and mixed voice/random-data traffic.

• Journal of the Korea Society for Simulation
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• v.25 no.4
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• pp.31-42
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• 2016

This study aims to identify the core technology for the automatic impact of the auto-sensing breaker that is one of the construction machinery which do not have a notable development success case yet in Korea. The study has been carried out as follows. Firstly, an analysis model was developed after determining the interconnection of pressure receiving area, opening area and port. And then, a simulation of situation that hard rock and soft rock are mixed was carried out to verify if it is possible to switch between long impact mode and short impact mode continuously. Lastly, the dynamic behavior of automatic control valve induced by the change of impact mode was analyzed based on the analysis result to decipher the core principle of automatic impact control.

• Journal of the Korea Society of Computer and Information
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• v.16 no.1
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• pp.143-151
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• 2011

Plaintext and key are independent in the existing block cipher. Also, encryption/decryption is performed by using structural features. Therefore, the external environment of suggested mixed cryptographic algorithm is identical with the existing ones, but internally, features of the existing block cipher were meant to be removed by making plaintext and key into dependent functions. Also, to decrease the loads on the authentication process, authentication add-on with dependent characteristic was included to increase the use of symmetric cryptographic algorithm. Through the simulation where the proposed cryptosystem was implemented in the chip level, we show that our system using the shorter key length than the length of the plaintext is two times faster than the existing systems.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.3300-3305
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• 2007

Ignition delay of second injection of HSDI diesel engine was usually much shorter than that of first injection. It is due to the interaction between radicals generated during the combustion process, and mixed gas of second injection. In this paper, To analyze combustion phenomena of multiple injection mode in HSDI diesel engine effectively, two-dimensional flamelet combustion model was modified. To reduce calculation time, two-dimensional flamelet equations were only applied near stoichiometric region. If this region was ignited, species and temperature of other region were changed to the steady-state solutions of one dimensional flamelet equations. By this method calculation time for solving flamelet equations was reduced to 20 percents, thought the results were almost same. Modified flamelet combustion model was coupled to commercial CFD code interactively using user subroutine.

• Proceedings of the KSME Conference
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• 2000.04a
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• pp.481-486
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• 2000

This paper presents vibration control performance of a passenger vehicle installed with olectro-rheological(ER) engine mounts. As a first step, a mixed-mode ER engine mount is modeled and manufactured. After verifying the controllability of the dynamic stiffness by the intensity of the electric field, ER engine mounts are incorporated with a full-car model. The governing equation of motion is then formulated by considering engine excitation force. A skyhook controller to attenuate vibration motions is designed. The controller is implemented through hardware-in-the-loop simulation and control responses are presented in the both frequency and time domains.

• Journal of Power Electronics
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• v.16 no.2
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• pp.778-785
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• 2016

An excess carrier lifetime extraction method is derived for physics-based insulated gate bipolar transistor (IGBT) models with consideration of the latest development in IGBT modeling. On the basis of the 2D mixed-mode Sentaurus simulation, the clamp turn-off test is simulated to obtain the tail current. The proposed excess carrier lifetime extraction method is then performed using the simulated data. The comparison between the extracted results and actual lifetime directly obtained from the numerical device model precisely demonstrates the accuracy of the proposed method.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1533-1546
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• 2015

This study presents a novel method for reducing the switching losses of an asymmetric half-bridge converter for a three-phase, 12/8 switched reluctance motor operated in low speed. In particular, this study aims to reduce the switching-off losses of chopping switches in the converter when operated in the current regulated mode (chopping mode). The proposed method uses the mixed parallel operation of IGBT (chopping switch) and MOSFET (auxiliary switch). MOSFET is precisely controlled to momentarily conduct prior to the turn-off interval of the IGBT. Consequently, the voltage across the switches is clamped to approximately zero, substantially decreasing the turn-off switching losses. The analytical expressions of power losses are extensively elaborated. Compared with the conventional asymmetric half-bridge converter, the modified converter can effectively minimize the switching losses. Therefore, the efficiency of the converter is eventually improved. Computer simulation and experimental results confirm the effectiveness of the proposed technique.

• The Journal of the Acoustical Society of Korea
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• v.18 no.2
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• pp.53-60
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• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.