• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.79-94
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• 2002

Root cause -Thermal expansion coefficient mismatch -Tape warpage -Initial die crack (die roughness) Guideline for failure prevention -Optimized tape/Substrate design for minimizing the warpage -Fine surface of die backside Root cause -Thermal expansion coefficient mismatch - Repetitive bending of a signal trace during TC cycle - Solder mask damage Guideline for failure prevention - Increase of trace width - Don't make signal trace passing the die edge - Proper material selection with thick substrate core Root cause -Thermal expansion coefficient mismatch -Creep deformation of solder joint(shear/normal) -Material degradation Guideline for failure Prevention -Increase of solder ball size -Proper selection of the PCB/Substrate thickness -Optimal design of the ball array -Solder mask opening type : NSMD -In some case, LGA type is better

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.14-14
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• 2011

Graphene is known to possess excellent thermal properties, including high thermal conductivity, that make it a prime candidate material for heat management in ultra large scale integrated circuits. For device applications, the key parameters are the thermal expansion coefficient and the thermal conductivity. There has been no reliable experimental determination on the thermal expansion coefficient of graphene whereas the estimates of the thermal conductivity vary widely. In this work, we estimate the thermal expansion coefficient of graphene on silicon dioxide by measuring the temperature dependence of the Raman spectrum. The shift of the Raman peaks due to heating or cooling results from both the intrinsic temperature dependence of the Raman spectrum of graphene and the strain on the graphene film due to the thermal expansion mismatch with silicon dioxide. By carefully comparing the experimental data against theoretical calculations, it is possible to determine the thermal expansion coefficient. The thermal conductivity is measured by estimating the thermal profile of a graphene film suspended over a circular hole of the substrate.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 춘계학술대회
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• pp.1315-1320
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• 2003

The thermal expansion coefficient, which causes the micro failure at the interfacial state of thin films is necessary to consider for proper designing MEMS. The effect of temperature on the coefficient of thermal expansion(CTE) of $SiO_2$ and $Si_3N_4$ film was investigated. Thermal strain induced by mismatch of CTE between substrate and thin film continuously measured with resolution-improved electronic speckle pattern interferometry(ESPI). The thermal stress induced by mismatch of CTE derivate through thermal strain. The thermal expansion coefficients of thin film were calculated with the general equation of CTE and thermal stress in thin films, and it confirmed that CTE of $SiO_2$changed from $0.25{\times}10^{-6}/^{\circ}C$ to $1.4{\times}10^{-6}/^{\circ}C$ with temperature increasing from 50 to $600^{\circ}C$

• 한국정밀공학회지
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• 제30권8호
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• pp.802-808
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• 2013

Thermal barrier coating (TBC) is used to protect substrates and extend the operating life of gas turbines in power plant and aeronautical applications. The major causes of failure of such coatings is spallation, which results from thermal stress due to a thermal expansion coefficient mismatch between the top coating and the bond coating layers. In this paper, the effects of the material properties and the thickness of the top coating layer on thermal stresses were evaluated using the finite element method and the equation for the thermal expansion coefficient mismatch stress. In addition, we investigated a design technique for the top coating whereby thermal resistance is exploited.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 1997년도 제26회 추계학술대회
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• pp.183-190
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• 1997

The wear behaviors of $Al_2O_3-40%TiO_2$ deposited on casting aluminum alloy(ASTM A356) by plasma spray against SiC ball have been investigated experimentally. Friction and wear tests are carried out at room temperature. The friction coefficient of $Al_2O_3-40%TiO_2$ coating is lower than that of pure $Al_2O_3$ coating(APS). It is found that low friction correspond to low wear and high friction to high wear in the experimental result. The thickness of $Al_2O_3-40%TiO_2$ coatings indicated the existence of the optimal coating thickness. It is found that a voids and porosities of coating surface result in the crack generated. As the tensile stresses in coating increased with the increased friction coefficient. The columnar grain of coating will be fractured to achieve the critical stress. It is found that the cohesive of splats and the porosity of surface play a role in wear characteristics. It is suggested that the mismatch of thermal expansion of substrate and coating play an important role in wear performance. Tensile and compressire under thermo-mechanical stress may be occurred by the mismatch between thermal expansion of substrate and coating. This crack propagation above interface is observed in SEM.

• Tribology and Lubricants
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• 제15권1호
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• pp.39-45
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• 1999

The wear behavior of $Al_2$O$_3$-40%TiO$_2$deposited on casted aluminum alloy (ASTM A356) by APS (Air Plasma Spray) against SiC ball has been investigated in this work. Wear tests were carried out at room temperature. The friction coefficient of $Al_2$O$_3$-40%TiO$_2$coating is lower than that of pure $Al_2$O$_3$coating(APS). $Al_2$O$_3$-40%TiO$_2$coating indicated the existence of the optimal coating thickness. It is found that voids and pores of coating surface resulted in the generation of cracks, and the cohesive of splats and the porosity of surface play a role in wear characteristics. It is suggested that the mismatch of thermal expansion of substrate and coating play an important role in wear performance. Tension and compression under thermo-mechanical stress may be occurred by the mismatch between thermal expansion of substrate and coating. The crack propagation above interface is observed in SEM.

• 마이크로전자및패키징학회지
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• 제24권1호
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 춘계학술대회 논문집
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• pp.42-42
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• 2010

We have characterized the previously undescribed parameters for engineering the electrical properties of single-walled carbon nanotube (SWCNT) films for technological applications. The surface tension of the top coating passivation material and matching coefficients of thermal expansion for the substrate and carbon nanotube network are two crucial parameters for the fabrication of reliable and highly conductive single-walled carbon nanotube network thin films.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.278-278
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• 2010

We have characterized the previously undescribed parameters for engineering the electrical properties of single-walled carbon nanotube (SWCNT) films for technological applications. The surface tension of the top coating passivation material and matching coefficients of thermal expansion for the substrate and carbon nanotube network are two crucial parameters for the fabrication of reliable and highly conductive single-walled carbon nanotube network thin films.

• Journal of Welding and Joining
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• 제32권3호
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• pp.68-73
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• 2014

Among through silicon via (TSV) technologies, for replacing Cu filling method, the method of molten solder filling has been proposed to reduce filling cost and filling time. However, because Sn alloy which has a high coefficient of thermal expansion (CTE) than Cu, CTE mismatch between Si and molten solder induced higher thermal stress than Cu filling method. This thermal stress can deteriorate reliability of TSV by forming defects like void, crack and so on. Therefore, we fabricated SiC composite filling material which had a low CTE for reducing thermal stress in TSV. To add SiC nano particles to molten solder, ball-typed SiC clusters, which were formed with Sn powders and SiC nano particles by ball mill process, put into molten Sn and then, nano particle-dispersed SiC composite filling material was produced. In the case of 1 wt.% of SiC particle, the CTE showed a lowest value which was a $14.8ppm/^{\circ}C$ and this value was lower than CTE of Cu. Up to 1 wt.% of SiC particle, Young's modulus increased as wt.% of SiC particle increased. And also, we observed cross-sectioned TSV which was filled with 1 wt.% of SiC particle and we confirmed a possibility of SiC composite material as a TSV filling material.