• Title/Summary/Keyword: minimum realization

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Development of Solar Energy-Underground Latent Heat Storage System for Greenhouse Heating (온실(溫室) 난방(暖房)을 위한 태양열(太陽熱)-지하(地下) 잠열(潛熱) 축열(蓄熱) 시스템 개발(開發))

  • Song, H.K.;Ryou, Y.S.
    • Journal of Biosystems Engineering
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    • v.19 no.3
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    • pp.211-221
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    • 1994
  • In this study, to maximize the solar energy utilization for greenhouse heating during the winter season, solar energy-underground latent heat storage system was constructed, and the thermal performance of the system has been analyzed to obtain the basic data for realization of greenhouse solar heating system. The results are summarized as follows. 1. $Na_2SO_4{\cdot}10H_20$ was selected as a latent heat storage material, its physical properties were stabilized and the phase change temperature was controlled at $13{\sim}15^{\circ}C$. 2. Solar radiation of winter season was the lowest value in December, and Jinju area was the highest and the lowest value was shown in Jeju area. 3. The minimum inner air temperature of greenhouse with latent heat storage system(LHSS) was $7.0{\sim}7.5^{\circ}C$ higher than that of greenhouse without LHSS and was $7.0{\sim}11.2^{\circ}C$ higher than the minimum ambient air temperature. 4. Greenhouse heating effect of latent heat storage system was getting higher according to the increase of solar radiation and was not concerned with the variation of minimum ambient air temperature. 5. The relative humidity of greenhouse with latent heat storage system was varied from 50 to 85%, but that of greenhouse without LHSS was varied from 30 to 93%. 6. The heating cost of greenhouse with solar energy-latent heat storage system was about 24% of that with the kerosene heating system.

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A Study on the Realization of a Digital Bit Synchronizer using the Gauss-Markov Estimation Technique (Gauss-Markov 추정 기법을 이용한 디지탈 비트 동기화기 실현에 관한 연구)

  • Bae, Hyeon-Deok;Ryu, Heung-Gyoon
    • The Journal of the Acoustical Society of Korea
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    • v.9 no.2
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    • pp.61-69
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    • 1990
  • We have investigated the digital bit synchronization problem in baseband communication receiver systems using the Gauss-Markov estimation technique which is equivalent to the weighted least square method. The realized bit synchronizer, including the data detector, processes the input signal two dimensionally into the transition phase and data level under the white Gaussian noise environment. We have confirmed the relization of the bit synchronizer via computer simulation. In addition, we have compared and evaluated the estimation error performance of the proposed method with that of the conventional DTTL method and of the minimum likelihood method.

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Design of Dynamic Time Warp Element for Speech Recognition (음성인식을 위한 Dynamic Time Warp 소자의 설계)

  • 최규훈;김종민
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.3
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    • pp.543-552
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    • 1994
  • Dynamic Time Warp(DTW) needs for iterative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at real time recognition design enables large dictionary hardware realization using DTW algorithm. The DTW PE cell separated into three large blocks. "MIN" is the one block for counting accumulated minimum distance. "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. Circuit design and verification about the three block have been accomplished, and performed layout '||'&'||' DRC(design rule check) using 1.2 m CMOS N-Well rule base.CMOS N-Well rule base.

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A Study on the Baseband Data Recovery and its Realization via the 2-Dimensional Transformantion of Estimation Parameters (추정 파라미터의 2차원 변환을 통한 기저대역 데이터 복원 및 그의 실현에 관한 연구)

  • 허동규;김기근;유흥균
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.15 no.12
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    • pp.1044-1052
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    • 1990
  • We have investigated the digital bit synchronization problem in baseband communication receiver systems using the Gauss-Markov estimation technique which is equivalent to the weighted least square method. The realized bit synchronizer, including the data detector, processes the input signal two dimensionally into the transition phase and data level under the white Gaussian noise environment. We have confrmed the realiation of the bit synchronizer via computer simulation. In addition, we have compared and evaluated the estimation error performance of the proposed method with that of the conventional DTTL method and of the minimum likelihood method.

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High Speed Position Control Method of a Linear DC Motor (리니어 직류 모터의 고속 위치 제어방식)

  • 엄기환;선동설;김주홍
    • The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.7 no.4
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    • pp.51-58
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    • 1993
  • This paper proposed a minmum time control method by a parabolic switching function to high speed position control, with high accuracy, of a Linear OC Motor A proposed method is organized simply and a bang-bang control's signal switched on a parabola type switching function in the phase for a minimum time control realization. However, a sliding mode occurs owing to system's modelling errors, so the minimum time control is realized a once switching bang-bang control by repeating trial experiments. Next time, in a neighborhood of the origin in the phase plane, a Linear OC Motor is stopped at the origin by the linear feedback control.

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A Study on the Status and Improvement of Domestic Marina Port Facility in Aspect of Navigators (항해자의 관점에서 본 국내 마리나 항만현황 및 개선방안에 관한 연구)

  • Jeong, Woo-Lee;Park, Jin-Soo
    • Journal of Navigation and Port Research
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    • v.38 no.1
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    • pp.73-79
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    • 2014
  • As Korean expanded the leisure time and improved the national incomes, the interest and demands of the marine leisure activities are increasing. However, it needs to considerate the infrastructure improvement for supporting these demands. This paper analyzed the problems based on the status of domestic marina port facilities including the absence of integrated management division and minimum standards for port facilities, governmental-centered administrative procedure, lack of professional manpower and linkage among educational institutes in aspect of navigators To improve these problems, this paper suggest that management system would be user-centered marina for marine leisure activities to make the integrated management division for marina port, the minimum standards for port facilities, realization of CIQ, familiarity for citizen and linkage among educational institutes.

A Study on the Self Tuning Control System for Servo Motor Drives (서보전동기 운전을 위한 자기동조제어 시스템에 관한 연구)

  • 오원석;이윤종
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.30B no.9
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    • pp.122-132
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    • 1993
  • In this paper, a self tuning control algorithm is proposed for the high performance drive of DC servo motor, which is adequate to the servo system having frequent load variation. In order to realization of the algorithm, the control system is developed using a fixed point high speed digital signal processor. TMS320C25. Control algorithm is composed of two parts. One is estimation law part using recursive least mean square method, the other is control law part using minimum variance control method. For the purpose of easiness of applying adaptive algorithm, developed control system is based o PC-DSP structure which can develop, debug programs and monitor the dynamic behaviors,etc. Through computer simulation and experimental results, it was verified that proposed control system could estimate system parameters and was robust to the variation of the load and as a result, was adequate to the servo motor drives.

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Fast Synthesis based on Ternary Universal Logic Module $U_h$ (3치 범용 논리 모듈 $U_h$에 의한 빠른 논리 합성)

  • 김영건;김종오;김흥수
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.1
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    • pp.57-63
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    • 1994
  • The logic function synthesis using ULM U$_h$ is constructed based on canonic Reed-Muller expansion coefficient for a given function. This paper proposes the fast synthesis algorithm using ULM U$_h$ for ternary function. By using circuit cost and synthesis method of proposed in this paper, order of control input variable minimum number of ULM U$_h$ can be decided in the synthesis of n-variable ternary function. Accordingly, this method enables to optimum circuit realization for ternary function synthesis using ULM ULM U$_h$ and can be applied to ternary function synthesis using ULM U$_h$. The complexity of search for select the order of all control input variables is (n+2)(n-1)/2.

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Backorder Policy of Multi-Supply Centers Distribution Chain for Capital-Goods Product (자본재 품목에 대한 다수 공급처 분배사슬의 부재고 정책)

  • Kim, Young-Sik;Hong, Sung-Jo;Choi, Jin-Yeong
    • IE interfaces
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    • v.13 no.3
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    • pp.438-443
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    • 2000
  • In this paper, we suggest a new backorder policy for stockout which is occurred in each regional distribution centers of distribution chain for capital-goods product. In backorder process of backorder policy, minimize expected stockout through the balancing-division module, and has occured stockout is backordering through the emergency supply from central distribution center and regional distribution center. Simulation tests show that our backorder policy is on the decrease of backorder cost and improvement of customer service. Our backorder policy has two important benefit. First, customer service level is improved by realization of minimum stockout. Second, the backorder process by allowance of the same level supply is to decrease system operating cost.

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On the Logical Simplification of Sequential Machines using Shift-Registers (쉬프트레지스터를 사용한 순서논리회로의 간단화에 관하여)

  • 이근영
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.15 no.4
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    • pp.7-13
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    • 1978
  • This paper is concerned with the realization of sequential machines using shift-register modules as their memory elements. Other methods were to select shift-registers under the specific conditions and didn't consider the complexity of combinational circuits driving them. By using an integer valued function, all shift-registers with minimum length could be selected and an optimum assignment with lowest complexity could be obtained by comparing the number of input lines of combinational logic circuits driving them.

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