• Title/Summary/Keyword: micro bump inspection

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An Accurate Boundary Detection Algorithm for Faulty Inspection of Bump on Chips (반도체 칩의 범프 불량 검사를 위한 정확한 경계 검출 알고리즘)

  • Joo, Ki-See
    • Proceedings of KOSOMES biannual meeting
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    • 2005.11a
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    • pp.197-202
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    • 2005
  • Generally, a semiconductor chip measured with a few micro units is captured by line scan camera for higher inspection accuracy. However, the faulty inspection requires an exact boundary detection algorithm because it is very sensitive to scan speed and lighting conditions. In this paper we propose boundary detection using subpixel edge detection method in order to increase the accuracy of bump faulty detection on chips. The bump edge is detected by first derivative to four directions from bump center point and the exact edge positions are searched by the subpixel method. Also, the exact bump boundary to calculate the actual bump size is computed by LSM(Least Squares Method) to minimize errors since the bump size is varied such as bump protrusion, bump bridge, and bump discoloration. Experimental results exhibit that the proposed algorithm shows large improvement comparable to the other conventional boundary detection algorithms.

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Accurate Boundary detection Algorithm for The Faulty Inspection of Bump On Chip (반도체 칩의 범프 불량 검사를 위한 정확한 경계 검출 알고리즘)

  • Kim, Eun-Seok
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.4
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    • pp.793-799
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    • 2007
  • Generally, a semiconductor chip measured with a few micro units is captured by line scan camera for higher inspection accuracy. However, the faulty inspection requires an exact boundary detection algorithm, because it is very sensitive to scan speed and lighting conditions. In this paper we propose boundary detection with subpixel edge detection in order to increase the accuracy of bump faulty detection on chips. The bump edge is detected by first derivative to four directions from bump center point and the exact edge positions are searched by the subpixel method. Also, the exact bump boundary to calculate the actual bump size is computed by LSM(Least Squares Method) to minimize errors since the bump size is varied such as bump protrusion, bump bridge, and bump discoloration. Experimental results exhibit that the proposed algorithm shows large improvement comparable to the other conventional boundary detection algorithms.

Detection of Flip-chip Bonding Error Through Edge Size Extraction of X-ray Image (X선 영상의 에지 추출을 통한 플립칩 솔더범프의 접합 형상 오차 검출)

  • Song, Chun-Sam;Cho, Sung-Man;Kim, Joon-Hyun;Kim, Joo-Hyun;Kim, Min-young;Kim, Jong-Hyeong
    • Journal of Institute of Control, Robotics and Systems
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    • v.15 no.9
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    • pp.916-921
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    • 2009
  • The technology to inspect and measure an inner structure of micro parts has become an important tool in the semi-conductor industrial field with the development of automation and precision manufacturing. Especially, the inspection skill on the inside of highly integrated electronic device becomes a key role in detecting defects of a completely assembled product. X-ray inspection technology has been focused as a main method to inspect the inside structure. However, there has been insufficient research done on the customized inspection technology for the flip-chip assembly due to the interior connecting part of flip chip which connects the die and PCB electrically through balls positioned on the die. In this study, therefore, it is implemented to detect shape error of flip chip bonding without damaging chips using an x-ray inspection system. At this time, it is able to monitor the solder bump shape by introducing an edge-extracting algorithm (exponential approximation function) according to the attenuating characteristic and detect shape error compared with CAD data. Additionally, the bonding error of solder bumps is automatically detectable by acquiring numerical size information at the extracted solder bump edges.

An Preliminary Technical Analysis of Developing Micro Bump Inspection System (초미세 범프 측정 시스템 개발을 위한 사전 기술 분석)

  • Yoo, Sunggeun;Song, Min-jeong;Park, Sangil;Cho, Sung-man;Jeon, So-yeon;Jeon, Ji-hye;Kim, Hee-tae;Myung, Chan-gyu;Park, Goo-man
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2017.11a
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    • pp.144-145
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    • 2017
  • 최근 전자 기기의 크기가 줄어들고 PCB의 사이즈와 반도체 패키지의 크기가 소형화되어 플립 칩 본딩(Flip chip bonding) 기술을 적용한 반도체 패키지 방식이 점점 늘어나고 있다. 이에 따라 PCB와 반도체 칩 사이를 연결하기 위해 응용되던 BGA(Ball Grid Array)에 핀 배열 대신 사용되는 범프(Bump)를 50um 이내의 초미세 범프로 만들어 일정한 배열을 유지하는 것이 중요하다. 또한 초미세 범프의 모양과 품질이 패키지 수율과 밀접하게 연관되기 때문에 이를 검사할 수 있는 기술이 필수적이다. 이에 본 논문은 초미세 범프측정을 할 수 있는 시스템 개발을 위한 측정 대상의 특징과 사용할 수 있는 광학계를 분석하였고, 획득된 영상을 가지고 딥러닝을 적용하여 정확하게 불량여부를 판별할 수 있는 초미세 범프 측정 시스템을 고안하였다.

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A Parallel Mode Confocal System using a Micro-Lens and Pinhole Array in a Dual Microscope Configuration (이중 현미경 구조를 이용한 마이크로 렌즈 및 핀홀 어레이 기반 병렬 공초점 시스템)

  • Bae, Sang Woo;Kim, Min Young;Ko, Kuk Won;Koh, Kyung Chul
    • Journal of Institute of Control, Robotics and Systems
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    • v.19 no.11
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    • pp.979-983
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    • 2013
  • The three-dimensional measurement method of confocal systems is a spot scanning method which has a high resolution and good illumination efficiency. However, conventional confocal systems had a weak point in that it has to perform XY axis scanning to achieve FOV (Field of View) vision through spot scanning. There are some methods to improve this problem involving the use of a galvano mirror [1], pin-hole array, etc. Therefore, in this paper we propose a method to improve a parallel mode confocal system using a micro-lens and pin-hole array in a dual microscope configuration. We made an area scan possible by using a combination MLA (Micro Lens Array) and pin-hole array, and used an objective lens to improve the light transmittance and signal-to-noise ratio. Additionally, we made it possible to change the objective lens so that it is possible to select a lens considering the reflection characteristic of the measuring object and proper magnification. We did an experiment using 5X, 2.3X objective lens, and did a calibration of height using a VLSI calibration target.